Robust design of threshold logic circuits using neuron MOS transistors

European Solid-State Device Research Conference

Volumn , Issue , 1998, Pages 592-595

  Luck, A ^a,b   Thewes, R ^a   Goser, K ^b   Weber, W ^a  

^a Corporate Technology ^*  (Germany)

^b TU DORTMUND UNIVERSITY   (Germany)

Author keywords

[No Author keywords available]

Indexed keywords

LOGIC GATES; THRESHOLD LOGIC;

MATCHING BEHAVIOR; MOSFETS; NEURON MOS TRANSISTORS; QUANTITATIVE KNOWLEDGE; ROBUST DESIGNS;

LOGIC DESIGN;

EID: 0342430198     PISSN: 19308876     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (3)

1. T. Shibata and T. Ohmi, IEEE TED, vol. 39, no. 6, pp. 1444-1455, June 1992.
2. K. Kotani, T. Shibata, and T. Ohmi in ISCAS, May 1996, pp. 205-208.
3. w. Weber, S. J. Prange, R. Thewes, E. Wohlrab, and A. Luck, IEEE TED, vol. 43, no. 10, pp. 1700-1708, October 1996.