VLSI considerations for TESH: A new hierarchical interconnection network for 3-D integration

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Volumn 6, Issue 3, 1998, Pages 346-353

  Jain, Vijay K ^a,b   Horiguchi, S ^c  

^a IEEE   (United States)

^b University of South Florida   (United States)

^c JAPAN ADVANCED INSTITUTE OF SCIENCE AND TECHNOLOGY   (Japan)

Author keywords

3 D integration; Defect tolerance; Hierarchical; Interconnection networks; Multicomputers; Reconfiguration; Routing; Tori connected meshes (TESH); Ultra large scale integration (ULSI); Vertical links; Very large scale integration (VLSI)

Indexed keywords

COMPUTATIONAL METHODS; DATA COMMUNICATION SYSTEMS; ELECTRIC NETWORK ANALYSIS; ELECTRIC NETWORK TOPOLOGY; INTEGRATED CIRCUIT LAYOUT; INTERCONNECTION NETWORKS; PERSONAL COMPUTERS; ROUTERS;

MULTICOMPUTER NETWORKS; TORI CONNECTED MESHES (TESH);

ULSI CIRCUITS;

EID: 0032167138     PISSN: 10638210     EISSN: None     Source Type: Journal    
DOI: 10.1109/92.711306     Document Type: Article

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