Measurement and characterization of multilayered interconnect capacitance for deep-submicron VLSI technology

IEEE Transactions on Semiconductor Manufacturing

Volumn 11, Issue 4, 1998, Pages 636-644

  Wee, Jae Kyung ^b   Park, Young June ^a,b   Min, Hong Shick ^b   Cho, Dae Hyung ^a,c   Seung, Man Ho ^d   Park, Hun Sup ^d  

^a IEEE

^b Seoul National University   (South Korea)

^c INTEL CORPORATION   (United States)

^d Hynix Semiconductor Inc   (South Korea)

Author keywords

[No Author keywords available]

Indexed keywords

CAPACITANCE; CAPACITANCE MEASUREMENT; COMPUTER AIDED DESIGN; COMPUTER SIMULATION; MATHEMATICAL MODELS; VLSI CIRCUITS;

MULTILAYERED INTERCONNECT;

CMOS INTEGRATED CIRCUITS;

EID: 0032203441     PISSN: 08946507     EISSN: None     Source Type: Journal    
DOI: 10.1109/66.728561     Document Type: Article

References (8)

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3. H. You and M. Soma, "Crosstalk analysis of interconnect lines and packages," IEEE Trans. Circuits Syst., vol. 37, pp. 1019-1026, Aug. 1990.
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6. Raphael User's Manual, Technology Modeling Associates, Inc., 1994.
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8. D. H. Cho, M. H. Seung, N. H. Kim, H. S. Park, J. K. Wee, Y. J. Park, and H. S. Min, "Measurement and characterization of multi-layered interconnect capacitance for deep submicron VLSI technology," in Proc. IEEE ICMTS 1997, pp. 91-94.