A new characterization of sub-μm parallel multilevel interconnects and experimental verification

IEEE Transactions on Semiconductor Manufacturing

Volumn 9, Issue 1, 1996, Pages 20-26

  Aoyama, Kimiko ^b   Ise, Kiyoshi ^b   Sato, Hisako ^b   Tsuneno, Katsumi ^b   Masuda, Hiroo ^a,b  

^a IEEE

^b HITACHI LTD   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

CAPACITANCE; INTEGRATED CIRCUIT LAYOUT; INTEGRATED CIRCUIT TESTING; MATHEMATICAL MODELS; PARALLEL PROCESSING SYSTEMS; TRANSMISSION LINE THEORY; VLSI CIRCUITS;

INTERCONNECT CAPACITANCE; PARALLEL MULTILEVEL INTERCONNECTS; TEST STRUCTURES;

INTERCONNECTION NETWORKS;

EID: 0030082941     PISSN: 08946507     EISSN: None     Source Type: Journal    
DOI: 10.1109/66.484279     Document Type: Article

References (6)

1. T. Sakurai et al., "Simple formula for two-and three-dimensional interconnects," IEEE Trans. Electron Devices, vol. ED-30, no. 2, pp. 183-185, Feb. 1983.
2. J. Chern et al., "Multilevel metal capacitance models for CAD design system," IEEE Electron Device Lett., vol. 13, no. 1, pp. 32-34, Jan. 1992.
3. K. Ichikawa et al., "Study of the wiring capacitance simulation in VLSI," Tech. Rep. ED93-81, SDM93-95, VLD93-36, pp. 45-51, Oct. 1993.
4. T. Toyabe, H. Masuda, Y. Aoki, H. Shukuri and K. Itoh, "Three-dimensional device simulator CADDETH with highly convergent matrix solution algorithms," IEEE Trans. Electron Devices, vol. ED-32, pp. 2038-2044, Oct. 1985.
5. Y. Ohkura, T. Toyabe and. H. Masuda, "Analysis of MOSFET capacitance and theri behavior at short-channel length using ac device simulator," IEEE Trons. Computer-Aided Design Integrated Circ., vol. CAD-6, pp. 423-430, May. 1987.
6. C. Gordon et al., "Time domain simulation of multiconductor transmission line with frequency-dependent losses," IEEE Trans. Computer-Aided Design, vol. 11, no. 11, pp. 1372-1387, Nov. 1992.