An extraction method to determine interconnect parasitic parameters

IEEE Transactions on Semiconductor Manufacturing

Volumn 11, Issue 4, 1998, Pages 615-623

  Chao, Chuan Jane ^b   Wong, Shyh Chyi ^a,c   Chen, Ming Jer ^a,b   Liew, Boon Khim ^d  

^a IEEE   (Taiwan)

^b NATIONAL CHIAO TUNG UNIVERSITY   (Taiwan)

^c WINBOND ELECTRONICS CORPORATION   (Taiwan)

^d TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY   (Taiwan)

Author keywords

[No Author keywords available]

Indexed keywords

CAPACITANCE; ELECTRIC RESISTANCE; INTEGRATED CIRCUIT MANUFACTURE; INTEGRATED CIRCUIT TESTING;

CHEMICAL MECHANICAL POLISHING; INTERCONNECT PARASITIC PARAMETER;

INTEGRATED CIRCUITS;

EID: 0032206608     PISSN: 08946507     EISSN: None     Source Type: Journal    
DOI: 10.1109/66.728559     Document Type: Article

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