Interconnection standard cell layouts

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Volumn 18, Issue 10, 1999, Pages 1512-1519

  For, Analysis ^a,b   Pedram, Massoud ^a,b   Preas, Bryan T ^a,b  

^a University of Southern California   (United States)

^b PALO ALTO RESEARCH CENTER   (United States)

Author keywords

Global route modeling; Interconnection length estimation; Layout area estimation; Placement modeling; Standard cell layout

Indexed keywords

COMPUTER AIDED DESIGN; INTEGRATED CIRCUIT LAYOUT; RANDOM PROCESSES;

STANDARD CELL LAYOUT;

INTERCONNECTION NETWORKS;

EID: 0033339153     PISSN: 02780070     EISSN: None     Source Type: Journal    
DOI: 10.1109/43.790628     Document Type: Article

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