Prediction of wiring space requirements for LSI

Proceedings - Design Automation Conference

Volumn , Issue , 1977, Pages 32-42

  Heller, W R ^a   Mikhail, W F ^a   Donath, W E ^b  

^a IBM   (United States)

^b IBM T J WATSON RESEARCH CENTER   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER AIDED DESIGN; HEURISTIC METHODS; STOCHASTIC SYSTEMS; LOGIC CIRCUITS; PROBABILITY;

AVERAGE LENGTH; AVERAGE NUMBERS; GLOBAL WIRING; HEURISTIC APPROACH; MODEL USE; SPACE REQUIREMENTS; WIRABILITY;

STOCHASTIC MODELS; INTEGRATED CIRCUITS;

EID: 0017445136     PISSN: 0738100X     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (10)

1. E. N. Gilbert, "Random Minimal Trees", SIAM J. Appi. Math. 13 (1965) pp. 376-387.
2. W. E. Donath, "Statistical Properties of the Placement of a Graph", SIAM J. Appi. Math. 16 (1968) pp. 376-387.
3. W. E. Donath, "Placement and Average Intercon-nection Lengths of Computer Logic", IBM Research Report 4610, to be published IEEE Journal of Solid State.
4. B. S. Landman and R. L. Russo, "On a Pin Versus Block Relationship for Partitions of Logic Graphs", IEEE Trans, on Computers C-20 (1971) pp. 14691479.
5. M. Feuer, "Connectivity of Random Logic", IBM Internal Report, 1974 (to be published).
6. W. E. Donath, "Equivalence of Memory to Random Logic", IBM Journal of Research and Development 18 (1974) pp. 401-407
7. see also "Stochastic Model of the Computer Logic Design Process", IBM Research Report RC 3136.
8. K. Khokhani and A. M. Patel, "The Chip Layout Problem: A Placement Procedure for LSI", Pro-ceedings 14th Design Automation Workshop, New Orleans, La, June 22, 1977.
9. I. Sutherland and D. Oestreicher, "How Big Should a Printed Circuit Board Be?", IEEE Trans, on Comp., May 1973, C-22, pp. 537-542.
10. K. A. Chen, M. Feuer, K. Khokhani, N. Nan, S. Schmidt, "The Chip Layout Problem: An Automatic Wiring Procedure", Proceedings 14th Design Automation Workshop, New Orleans, La, June 22, 1977.