Accurate prediction of physical design characteristics for random logic

Proceedings - IEEE International Conference on Computer Design: VLSI in Computers and Processors

Volumn , Issue , 1989, Pages 100-108

  Pedram, Massoud ^a   Preas, Bryan ^a  

^a UNIVERSITY OF CALIFORNIA   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

INTEGRATED CIRCUITS--LAYOUT; PROBABILITY--RANDOM PROCESSES;

FLOORPLANNING; INTERCONNECTION LENGTHS; LAYOUT AREAS; OPTIMIZED PLACEMENTS; RANDOM LOGIC; STANDARD CELL LAYOUTS;

LOGIC DESIGN;

EID: 0024886722     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (21)