On a Pin Versus Block Relationship For Partitions of Logic Graphs

IEEE Transactions on Computers

Volumn C-20, Issue 12, 1971, Pages 1469-1479

  Landman, Bernard S ^a   Russo, Roy L ^a  

^a IBM T J WATSON RESEARCH CENTER   (United States)

Author keywords

Hardware implementation; logic package pin requirements; logic partitioning; pins versus blocks relation; pins versus circuits relation

Indexed keywords

LOGIC CIRCUITS;

COMPUTERS, DIGITAL--LOGIC DESIGN;

EID: 0015206785     PISSN: 00189340     EISSN: None     Source Type: Journal    
DOI: 10.1109/T-C.1971.223159     Document Type: Article

References (11)

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8. C. E. Radke, “A justification of and an improvement on a useful rule for predicting circuit-to-pin ratios,” in Proc. 6th Annu. SHARE/Ass. Comput. Mach./IEEE Design Automation Workshop, June 8–12, 1969.
9. W. E. Donath, “Hierarchical structure of computers,” IBM T. J. Watson Res. Cen., Yorktown Heights, N. Y., Rep. RC 2392, Mar. 1969.
10. R. B. Hitchcock, “Partitioning of logic graphs: A theoretical analysis of pin reduction,” in Proc. 7th Annu. Share/Ass. Comput. Mach./IEEE Design Automation Workshop, June 22-24, 1960.
11. A. Mennone and R. L. Russo, “Mapping of computer logic: Experiments using the encoding concept to reduce module require-ments,‘” to be published.