Techniques for Area Estimation of VLSI Layouts

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Volumn 8, Issue 1, 1989, Pages 81-92

  Kurdahi, Fadi J ^a   Parker, Alice C ^b  

^a UNIVERSITY OF CALIFORNIA   (United States)

^b UNIVERSITY OF SOUTHERN CALIFORNIA   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

PROBABILITY;

CELL AREA ESTIMATION; PROBABILISTIC MODELS; STANDARD CELL DESIGN;

INTEGRATED CIRCUITS, VLSI;

EID: 0024479018     PISSN: 02780070     EISSN: 19374151     Source Type: Journal    
DOI: 10.1109/43.21821     Document Type: Article

References (17)

1. S. Muroga, VLSI Systems Design. New York: Wiley-Interscience, 1982.
2. S. Sastry, “Wireability analysis of integrated circuits,” Ph.D. dissertation, Univ. of Southern California, Jan. 1985.
3. W.R. Heller et al., “Prediction of wiring space requirements for LSI,” Design Automation and Fault Tolerant Computing, vol. 2, pp. 117–144, May 1978.
4. B. Landman and R. Russo, “On a pin versus block relationship for partitioning of logic graphs,” IEEE Trans. Comput., vol. C-20, pp. 1469–1478, Dec. 1971.
5. W.R. Heller et al. “Prediction of wiring space requirements for LSI,” in IEEE/ACM Proc. 14th Design Automation Conf., pp. 20–22, June 1977.
6. M. Feuer, “Connectivity of random logic,” IEEE Trans. Comput., vol. C-31, pp. 29–33, Jan. 1982.
7. A. El Gamal, “Two-dimensional stochastic model for interconnections in master slice integrated circuits,” IEEE Trans. Circuits Syst., vol. CAS-28, pp. 127–138, Feb. 1981.
8. B.D. Richard, “A standard cell initial placement strategy,” in IEEE/ ACM Proc. 21st Design Automation Conf., pp. 392–398, June 1984.
9. S. Kang, “Linear ordering and application to placement,” in IEEE/ ACM Proc. 20th Design Automation Conf, pp. 457–464, July 1983.
10. K. Ueda H. Kitazawa, and I. Harada, “CHAMP: chip floor plan for hierarchical VLSI layout design,” IEEE Trans. Computer-Aided Design, vol. CAD-4, pp. 12–22, Jan. 1985.
11. D. SchulerandE. Ulrich, “Clustering and linear placement,” in Proc. 9th Design Automation Workshop, pp. 50–56, July 1972.
12. K. Supowit, “Reducing channel density in standard cell layout,” in IEEE/ACM Proc. 20th Design Automation Conf, pp. 263–269, June 1983.
13. A. Feller and R. Noto, “A speed oriented, fully-automatic layout program for random logic VLSI devices,” in AF1PS Conf. Proc., pp. 303–311, vol. 47, June 1978.
14. L. Haferand A. Parker, “A formal method for the specification analysis, and design of register-transfer level digital logic,” IEEE Trans. Computer-Aided Design, vol. CAD-2, pp. 4–17, Jan. 1983.
15. F.J. Kurdahi, “Area estimation of VLSI circuits,” Ph.D. dissertation, Univ. of Southern California, Aug. 1987.
16. J. Granacki and A. Parker, “The effect of register-transfer design tradeoffs on chip area and performance,” in IEEE/ACM Proc. 20th Design Automation Conf., pp. 419–424, June 1983.
17. N. Park, “Synthesis of high speed digital systems,” Ph.D. dissertation, Univ. of Southern California, Aug. 1985.