Stochastic Models for Wireability Analysis of Gate Arrays

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Volumn 5, Issue 1, 1986, Pages 52-65

  Sastry, Sarma ^a   Parker, Alice C ^a  

^a UNIVERSITY OF SOUTHERN CALIFORNIA   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

INTEGRATED CIRCUITS - COMPUTER AIDED DESIGN; PROBABILITY;

GATE ARRAYS; LARGE LSI/VLSI SYSTEMS; WIRABILITY ANALYSIS;

INTEGRATED CIRCUITS, VLSI;

EID: 0022593949     PISSN: 02780070     EISSN: 19374151     Source Type: Journal    
DOI: 10.1109/TCAD.1986.1270177     Document Type: Article

References (10)

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4. A. EL-Gamal, “Two-dimensional stochastic model for interconnections in master slice integrated circuits,” IEEE Trans. Circuits Syst., CAS-28, no. 2, pp. 127–138, Feb. 1981.
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9. S. Sastry, “Wireability analysis of integrated circuits,” Tech. Rep. DISC/85-2, Dep. Elec. Engin.-Syst., Univ. of Southern California, Los Angeles, Oct. 1985
10. I. E. Sutherland and D. Oestreicher, “How big should a printed circuit board be?;” IEEE Trans. Comput., C-22, pp. 537–542, May 1973.