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Volumn 46, Issue 6 PART 1, 1999, Pages 1434-1439

Single event effects in static and dynamic registers in a 0.25im CMOS technology

Author keywords

[No Author keywords available]

Indexed keywords

APPLICATION SPECIFIC INTEGRATED CIRCUITS; CMOS INTEGRATED CIRCUITS; COMPUTER SIMULATION; DOSIMETRY; ELECTRIC NETWORK TOPOLOGY; ELECTRIC POWER SUPPLIES TO APPARATUS; FLIP FLOP CIRCUITS; SHIFT REGISTERS;

EID: 0033307440     PISSN: 00189499     EISSN: None     Source Type: Journal    
DOI: 10.1109/23.819104     Document Type: Article
Times cited : (47)

References (11)
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    • October 5-9,1998, Villa Olmo, Como, Italy, to be published in NIM.
    • P. larron et al., "Deep Submicron CMOS Technologies for the LHC Experiment, presented at the . 6th International Conference on Advanced Technology and Particles Physics, October 5-9,1998, Villa Olmo, Como, Italy, to be published in NIM.
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    • R. Velazco, D. Bessot, S. Duzellier, R. Ecoffet, R. Koga, "2 CMOS Memory Cells Suitable for the Design of SEUTolerant VLSI Circuits", IEEE Trans. Nucl. Science, Vol.41, No.6, p.2229, December 1994.
    • IEEE Trans. Nucl. Science
    • Velazco, R.1    Bessot, D.2    Duzellier, S.3    Ecoffet, R.4    Koga, R.5
  • 8
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    • "Upset Hardened Memory Design for Submicron CMOS Technology"
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* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.