Double-island single-electron devices - a useful unit device for single-electron logic LSI's

IEEE Transactions on Electron Devices

Volumn 46, Issue 5, 1999, Pages 954-959

  Fujiwara, Akira ^a   Takahashi, Yasuo ^a   Yamazaki, Kenji ^a   Namatsu, Hideo ^a   Nagase, Masao ^a   Kurihara, Kenji ^a   Murase, Katsumi ^a  

^a Bio Medical Informatics Research Center   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

ELECTRON TUNNELING; LSI CIRCUITS; NANOTECHNOLOGY; SEMICONDUCTOR QUANTUM DOTS; SILICON ON INSULATOR TECHNOLOGY;

DOUBLE-ISLAND SINGLE-ELECTRONS DEVICES;

LOGIC CIRCUITS;

EID: 0032687552     PISSN: 00189383     EISSN: None     Source Type: Journal    
DOI: 10.1109/16.760403     Document Type: Article

References (15)

1. N. Asahi M. Akazawa and Y. Amemiya "Binary-decision-diagram device" IEEE Trans. Electron Devices vol. 42 pp. 1999-2003 Nov. 1995; and "Single-electron logic device based on the binary-decision-diagram device" IEEE Trans. Electron Devices vol. 44 pp. 1109-1116 July 1997.
2. K. Yano T. Ishii T. Hashimoto T. Kobayashi F. Murai and K. Seki "Room-temperature single-electron memory" IEEE Trans. Electron Devices vol. 41 pp. 1628-1637 Sept. 1994.
3. L.G. Guo E. Leobandung and S.Y. Chou "A silicon single-electron transistor memory operating at room temperatures" Science vol. 275 pp. 649-651 1997.
4. A. Nakajima T. Futatsugi K. Kosemura T. Fukano and N. Yokoyama "Room temperature operation of Si single-electron memory with self-aligned floating dot gate" Appl. Phys. Lett. vol. 70 pp. 1742-1744 1997.
5. Y. Takahashi M. Nagase H. Namatsu K. Kurihara K. Iwadate Y. Nakajima S. Horiguchi K. Murase and M. Tabe "Fabrication technique for Si single-electron transistor operating at room temperature" Electron. Lett. vol. 31 pp. 938-940 1994.
6. Y. Takahashi H. Namatsu K. Kurihara K. Iwadate M. Nagase and K. Murase "Size dependence of the characteristics of Si single-electron transistor on SIMOX substrates" IEEE Trans. Electron Devices vol. 43 pp. 1213-1217 Aug. 1996.
7. A. Fujiwara Y. Takahashi K. Murase and M. Tabe "Time-resolved measurement of single-electron tunneling in a Si single-electron transistor with satellite Si islands" Appl. Phys. Lett. vol. 67 pp. 2957-2959 1995.
8. H. Ishikuro T. Fujii T. Saraya G. Hashiguchi T. Hiramoto and T. Ikoma "Coulomb blockade oscillations at room temperature in a Si quantum wire metal-oxide-semiconductor field-effect transistor fabricated by anisotropic etching on a silicon-on-insulator substrate" Appl. Phys. Lett. vol. 68 pp. 3585-3587 1996.
9. L.J. Geerligs V.J. Anderegg P.A.M. Holweg J.E. Mooji H. Pothier D. Esteve C. Urbina and M.H. Devoret "Frequency-locked turnstile device for single electrons" Phys. Rev. Lett. vol. 64 pp. 2691-2694 1990.
10. H. Pothier P. Lafarge R.F. Orfila C. Urbina D. Esteve and M.H. Devoret "Single electron pump fabricated with ultrasmall normal tunnel junctions" Phys. B vol. 169 pp. 573-574 1991.
11. F. Hofmann T. Heinzel D.A. Wharam J.P. Kotthaus G. Böhm W. Klein G. Tränkle and G. Weimann "Single electron switching in a parallel quantum dot" Phys. Rev. B vol. 51 pp. 13872-13875 1995.
12. M. Nagase T. Ishiyama and K. Murase "Surface morphology of SIMOX-Si layers characterized using atomic force microscopy" in Proc. 6th Int. Symp. SOI Technology and Devices The Electrochemical Society Pennington NJ 1994 pp. 191-196.
13. J.R. Tucker "Complementary digital logic based on the Coulomb blockade" J. Appl. Phys. vol. 72 pp. 4399-4413 1992.
14. A. Fujiwara Y. Takahashi H. Namatsu K. Kurihara and K. Murase "Suppression of effects of parasitic metal-oxide-semiconductor field-effect transistors on Si single-electron transistors" Jpn.J. Appl. Phys. vol. 37 no. 6 1998 in press.
15. K.K. Likharev "Single-electron transistors: Electrostatic analogs of the DC squids" IEEE Trans. Magn. vol. MAG-23 pp. 1142-1145 1987.