Derivation of Signal Flow Direction in MOS VLSI

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Volumn 6, Issue 3, 1987, Pages 480-490

  Jouppi, Norman P ^a  

^a HEWLETT PACKARD COMPANY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

LOGIC DESIGN; MATHEMATICAL TECHNIQUES - HEURISTIC; SEMICONDUCTOR DEVICES, MOS - COMPUTER SIMULATION;

ELECTRICAL RULES CHECKER; SIGNAL FLOW DIRECTION DERIVATION; TIMING VERIFIER (TV);

INTEGRATED CIRCUITS, VLSI;

EID: 0023347724     PISSN: 02780070     EISSN: 19374151     Source Type: Journal    
DOI: 10.1109/TCAD.1987.1270295     Document Type: Article

References (11)

1. J. Hennessy, N. Jouppi, S. Przybylski, C. Rowen, and T. Gross, “Design of a high performance VLSI processor,” in Proc. of the Third Coifech VLSI Conf. , Mar. 1983, pp. 33–54.
2. S. Przybylski, “Design verification and testing of MIPS,” in Proc. of the MIT Conf. on Advanced Research in VLSI, Jan. 1984, pp. 100–109.
3. N. P. Jouppi, “Timing verification and performance improvement of MOS VLSI designs.” Ph.D. dissertation, Stanford Univ., June 1984.
4. J. K. Ousterhout, “Crystal: A timing analyzer for nMOS VLSI circuits,” in Proc. of the Third Caltech VLSI Conf., 1983, pp. 57–69.
5. N. P. Jouppi, “TV: An nMOS timing analyzer,” in Proc. of the Third Caltech VLSI Conf., Mar. 1983, pp. 71–85.
6. J. K. Ousterhout, “A switch-level timing verifier for digital MOS VLSI,” IEEE Trans. Computer-Aided Design, vol. CAD-4, no. 3. pp. 336–348, July 1985.
7. R. E. Bryant, “MOSSIM: A switch level simulator for MOS LSI,” in Proc. of the 18th Design Automation Conf., June 1981. pp. 786–790.
8. N. P. Jouppi, “Timing analysis for nMOS VLSI.” in Proc. of the 20th Design Automation Cont (Miami Beach), June 1983, pp. 411–418. 418.
9. J. H. Clark, “The geometry engine: A VLSI geometry system for graphics,” in Proc. SIGGRAPH '82, 1982.
10. G. Louie, T. Ho, and E. Cheng. “The MicroVAX I data path chip,” VLSI Design, vol. 4. no. 8, pp. 14–21, Dec. 1983.
11. R. Sherburne M. Katevenis, D. Patterson, and C. Sequin. “Datapath design for RISC.” in Proc. Conf. on Advanced Research in VLSI, Jan. 1982, pp. 53–62.