PLL-based programmable clock generator with 50- to 350-MHz oscillating range for video signal processors

IEICE Transactions on Electronics

Volumn E77-C, Issue 12, 1994, Pages 1951-1956

  Goto, Junichi ^a   Yamashina, Masakazu ^a   Inoue, Toshiaki ^a   Shih, Benjamin S ^a   Koseki, Youichi ^a   Horiuchi, Tadahiko ^a   Hamatake, Nobuhisa ^a   Kumagai, Kouichi ^a   Enomoto, Tadayoshi ^a   Yamada, Hachiro ^a  

^a NEC CORPORATION   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

CMOS INTEGRATED CIRCUITS; FREQUENCY DIVIDING CIRCUITS; FREQUENCY MULTIPLYING CIRCUITS; LSI CIRCUITS; PHASE LOCKED LOOPS; SIGNAL GENERATORS; TIMING CIRCUITS; VARIABLE FREQUENCY OSCILLATORS; VIDEO SIGNAL PROCESSING;

CONTROL VOLTAGE GENERATOR; PHASE DETECTOR; PROGRAMMABLE CLOCK GENERATOR; PROGRAMMABLE DIVIDER;

ELECTRIC CLOCKS;

EID: 0028730343     PISSN: 09168524     EISSN: None     Source Type: Journal    
DOI: None     Document Type: Article

References (5)