Low-power digital PLL with one cycle frequency lock-in time for clock syntheses up to 100 MHz using 32,768 Hz reference clock

Proceedings of the Annual IEEE International ASIC Conference and Exhibit

Volumn , Issue , 1996, Pages 291-294

  Fried, Rafael ^a  

^a EPFL   (Switzerland)

Author keywords

[No Author keywords available]

Indexed keywords

DIGITAL CIRCUITS; ELECTRIC CLOCKS; ELECTRIC NETWORK SYNTHESIS; FREQUENCIES; GAIN CONTROL; OSCILLATORS (ELECTRONIC);

ADVANCED POWER MANAGEMENT; CLOCK SYNTHESES; CYCLE FREQUENCY LOCK IN TIME; DIGITAL PHASE LOCKED LOOPS; REFERENCE FREQUENCY;

PHASE LOCKED LOOPS;

EID: 0029764248     PISSN: 10630988     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (13)