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Volumn 29, Issue 3, 1994, Pages 271-279

Cell-Based Fully Integrated CMOS Frequency Synthesizers

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER CIRCUITS; FREQUENCY SYNTHESIZERS;

EID: 0028385043     PISSN: 00189200     EISSN: 1558173X     Source Type: Journal    
DOI: 10.1109/4.278348     Document Type: Article
Times cited : (81)

References (10)
  • 3
    • 0003857807 scopus 로고
    • Design, & Applications. New York: McGraw-Hill
    • R. E. Best, Phase-Locked Loops Theory, Design, & Applications. New York: McGraw-Hill, 1984, p. 8.
    • (1984) Phase-Locked Loops Theory , pp. 8
    • Best, R.E.1
  • 5
    • 0019079092 scopus 로고
    • Charge-pump phase-lock loops
    • Nov.
    • F. M. Gardner, “Charge-pump phase-lock loops,” IEEE Trans. Commun., vol. COM-28, pp. 1849-1858, Nov. 1980.
    • (1980) IEEE Trans. Commun. , vol.COM-28 , pp. 1849-1858
    • Gardner, F.M.1
  • 7
    • 0025550911 scopus 로고
    • A 30-MHz hybrid analog/digital clock recovery circuit in 2-µm CMOS
    • Dec.
    • B. Kim, D. N. Helman, and P. R. Gray, “A 30-MHz hybrid analog/digital clock recovery circuit in 2-µm CMOS,” IEEE J. Solid-State Circuits, vol. 25, pp. 1385-1394, Dec. 1990.
    • (1990) IEEE J. Solid-State Circuits , vol.25 , pp. 1385-1394
    • Kim, B.1    Helman, D.N.2    Gray, P.R.3
  • 8
    • 0026954972 scopus 로고
    • A PLL clock generator with 5 to 110 MHz of lock range for microprocessors
    • Nov.
    • I. A. Young, J. K. Greason, and K. L. Wong, “A PLL clock generator with 5 to 110 MHz of lock range for microprocessors,” IEEE J. Solid-State Circuits, vol. 27, pp. 1599-1607, Nov. 1992.
    • (1992) IEEE J. Solid-State Circuits , vol.27 , pp. 1599-1607
    • Young, I.A.1    Greason, J.K.2    Wong, K.L.3


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.