3.3 V all digital phase-locked loop with small DCO hardware and fast phase lock

Proceedings - IEEE International Symposium on Circuits and Systems

Volumn 3, Issue , 1998, Pages 554-557

  Chiang, Jen Shiun ^a   Chen, Kuang Yuan ^a  

^a TAMKANG UNIVERSITY   (Taiwan)

Author keywords

[No Author keywords available]

Indexed keywords

CMOS INTEGRATED CIRCUITS; COMPUTER SIMULATION; COST EFFECTIVENESS; DIGITAL CONTROL SYSTEMS; ERROR ANALYSIS; INTEGRATED CIRCUIT LAYOUT; MICROPROCESSOR CHIPS; OSCILLATORS (ELECTRONIC); SYSTEM STABILITY; TIMING CIRCUITS; TRANSISTORS;

ALL DIGITAL PHASE-LOCKED LOOP (ADPLL) CIRCUITS; DIGITAL CONTROL OSCILLATORS (DCO); REFERENCE CLOCK FREQUENCY;

PHASE LOCKED LOOPS;

EID: 0031642059     PISSN: 02714310     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (11)