A PLL Clock Generator with 5 to 110 MHz of Lock Range for Microprocessors

IEEE Journal of Solid-State Circuits

Volumn 27, Issue 11, 1992, Pages 1599-1607

  Young, Ian A ^a   Greason, Jeffrey K ^a   Wong, Keng L ^a  

^a INTEL CORPORATION   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CMOS INTEGRATED CIRCUITS; LOGIC CIRCUITS; LOW PASS FILTERS; MICROPROCESSOR CHIPS; PHASE LOCKED LOOPS; TRANSFER FUNCTIONS;

ANALOG PLL; LOOP FILTER; MICROPROCESSOR CLOCK GENERATOR; PICK-TO-PICK JITTER; PLL CLOCK GENERATOR; VOLTAGE-CONTROLLED RESISTOR;

TIMING CIRCUITS;

EID: 0026954972     PISSN: 00189200     EISSN: 1558173X     Source Type: Journal    
DOI: 10.1109/4.165341     Document Type: Article

References (5)

1. J. Schutz, “A 100 MHz microprocessor,” in ISSCC 1991 Dig. Tech. Papers, pp. 90-91.
2. B. Kim and P. Gray, “A 30 MHz hybrid analog/digital clock recovery circuit in 2-μm CMOS,” IEEE J. Solid-State Circuits, vol. 25, pp. 1385-1394, Dec. 1990.
3. M. Johnson and E. Hudson, “A variable delay line PLL for CPU-coprocessor synchronization,” IEEE J. Solid-State Circuits, vol. 23, pp. 1218-1223, Oct. 1988.
4. G. Moon, M. Zaghloul, and R. Newcomb, “An enhancement-mode voltage-controlled linear resistor with large dynamic range,” IEEE Trans. Circuit Syst., vol. 37, p. 1284, Oct. 1990.
5. F. A. Gardner, “Charge pump phase locked loops,” IEEE Trans. Commun., vol. COM-28, pp. 1849-1858, Nov. 1980.