A 0.4 μm gate-all-around tft (gat) using a dummy nitride pattern for high-density memories

Japanese Journal of Applied Physics

Volumn 34, Issue 2S, 1995, Pages 895-899

  Maegawa, Shigeto ^a   Ipposhi, Takashi ^a   Maeda, Shigenobu ^a   Nishimura, Hisayuki ^a,b   Tanina, Osamu ^a   Kuriyama, Hirotada ^a   Inoue, Yasuo ^a   Nishimura, Tadashi ^a   Tsubouchi, Natsuro ^a  

^a MITSUBISHI ELECTRIC CORPORATION   (Japan)

^b Ryoden Semiconduct Syst Eng Corp   (Japan)

Author keywords

Double gate transistor; Gate all around structure; LCD; SRAM; TFT

Indexed keywords

ELECTRIC CONTACTS; ELECTRIC RESISTANCE; GATES (TRANSISTOR); LEAKAGE CURRENTS; LIQUID CRYSTAL DISPLAYS; MOSFET DEVICES; OXIDATION; POLYCRYSTALLINE MATERIALS; RANDOM ACCESS STORAGE; SEMICONDUCTING SILICON; SEMICONDUCTOR DEVICE MANUFACTURE;

CHANNEL CONDUCTANCE; CHANNEL POLYSILICON; DOUBLE GATE TRANSISTOR; DUMMY NITRIDE PATTERN; GATE ALL AROUND STRUCTURE; HIGH DENSITY MEMORIES; STATIC RANDOM ACCESS MEMORY; SUB HALF MICRON REGIME;

THIN FILM TRANSISTORS;

EID: 0029252426     PISSN: 00214922     EISSN: 13474065     Source Type: Journal    
DOI: 10.1143/JJAP.34.895     Document Type: Article

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