A Stacked Split Word-Line (SSW) cell for low voltage operation, large capacity, high speed SRAMs

Technical Digest - International Electron Devices Meeting, IEDM

Volumn , Issue , 1993, Pages 809-812

  Keda, Shuji ^a   Asayama, Kyoichiro ^a   Hashimoto, Naotaka ^a   Fujita, Eri ^a   Yoshida, Yasuko ^a   Koike, Atsuyosi ^a   Yamanaka, Toshiaki ^a   Ishibashi, Koichiro ^a   Meguro, Satoshi ^a  

^a HITACHI LTD   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

CYTOLOGY; RADIATION HARDENING; STATIC RANDOM ACCESS STORAGE; THRESHOLD VOLTAGE; TRANSISTORS; CAPACITORS; CELLULAR ARRAYS; MASKS; THIN FILM CIRCUITS;

CELL STABILITY; CELL TECHNOLOGY; GATE THIN FILMS; HIGH SPEED; I-LINE STEPPERS; LOW VOLTAGE OPERATION; OPTIMISATIONS; SMALL CELLS; SOFT ERROR; TOP GATE;

CELLS; RANDOM ACCESS STORAGE;

ACCESS TRANSISTORS; PULL DOWN TRANSISTORS; STACKED SPLIT WORD LINE CELL (SSW);

EID: 0027816554     PISSN: 01631918     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (6)

1. K. Itabashi et al., "A Split Wordline Cell for 16Mbit SRAM Using Polysilicon Sidewall Contacts," IEDM. Tech. Dig., pp 477-480, 1991
2. H. Ohkubo et al., "16Mbit SRAM Cell Technology for 2.0V Operation," IEDM. Tech. Dig., pp. 481-484, 1991
3. J.D. Hayden et al., "A High-Performance Quadruple Well, Quadruple Poly BiCMOS Process for Fast 16Mb SRAMs," IEDM. Tech. Dig., pp. 819-822, 1992
4. S. Ikeda et al., "Polysilicon Transistor technology for Large Capacity SRAMs," IEDM. Tech. Dig., pp. 469-472, 1990
5. K. Ishibashi et al., "A 12.5ns 16Mb CMOS SRAM," Symp. on VLSI Circuits, Tech. Dig., pp 103-104, 1993
6. C. M. Hashimoto, H. Miura, K. Asayama, H. Ohta, S. Ikeda, "Dislocation Free Gate Process using In-situ Doped Polysilicon Thin Films by Considering Crystallization-induced Stress of the Films" Device Research Conference, Session IV B-4, 1993