A Single-Bit-Line Cross-Point Cell Activation (SCPA) Architecture for Ultra-Low-Power SRAM's

IEEE Journal of Solid-State Circuits

Volumn 28, Issue 11, 1993, Pages 1114-1118

  Ukita, Motomu ^a   Murakami, Shuji ^a   Yamagata, Tadato ^a   Kuriyama, Hirotada ^a   Nishimura, Yasumasa ^a   Anami, Kenji ^a  

^a MITSUBISHI ELECTRIC CORPORATION   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

CMOS INTEGRATED CIRCUITS; ELECTRIC POWER SUPPLIES TO APPARATUS; INTEGRATED CIRCUIT LAYOUT; MICROPROCESSOR CHIPS; MOS DEVICES; SEMICONDUCTOR DEVICE MANUFACTURE; SEMICONDUCTOR DEVICE STRUCTURES;

BOOST CIRCUIT; CMOS WAFER PROCESS TECHNOLOGY; PMOS; SINGLE BIT LINE CROSS POINT CELL ACTIVATION; STATIC RANDOM ACCESS MEMORY; ULTRA LOW POWER;

RANDOM ACCESS STORAGE;

EID: 0027693918     PISSN: 00189200     EISSN: 1558173X     Source Type: Journal    
DOI: 10.1109/4.245590     Document Type: Article

References (3)

1. M. Yoshimoto et al.,“A divided word-line structure in static RAM and its application to 64-k full CMOS RAM,” IEEE J. Solid-State Circuits, vol. SC-18, pp. 479–485, Oct. 1983.
2. R. G. Stewart and A. G. F. Dingwall, “16-k CMOS/SOS asynchronous static RAM,” in ISSCC Dig. Tech. Papers, pp. 104–105, Feb. 1979.
3. F. Hayashi and M. Kitakata, “A high performance polysilicon TFT using RTA and plasma hydrogenation applicable to highly stable SRAM’s of 16 Mb and beyond,” in Symp. VLSI Technology Dig. Tech. Papers, pp. 36–37, June 1992.