An asymmetric memory cell using a C-TFT for ULSI SRAMs

Digest of Technical Papers - Symposium on VLSI Technology

Volumn 1992-June, Issue , 1992, Pages 38-39

  Kurivama, H ^a   Okada, T ^a   Ashida, M ^a   Sakamoto, O ^a   Yuzuriha, K ^a   Tsutsunii, K ^a   Nishimura, T ^a   Anatni, K ^a   Kohno, H ^a   Miyoshi, Y ^a  

^a MITSUBISHI ELECTRIC CORPORATION   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

FIELD EFFECT TRANSISTORS; MEMORY ARCHITECTURE; SEMICONDUCTOR STORAGE; STATIC RANDOM ACCESS STORAGE; ULSI CIRCUITS;

BOTTOM GATE; CELL SIZE; LOW SUPPLY VOLTAGES; MEMORY CELL; N-CHANNEL; P CHANNELS; READ OPERATION; SRAM MEMORY CELLS;

THIN FILM TRANSISTORS;

EID: 52949088546     PISSN: 07431562     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/VLSIT.1992.200635     Document Type: Conference Paper

References (4)

1. T.Yamanaka et al., IEDM. Tech. Dig., P.477 (1990).
2. K.Itabashi et al., IEDM, Tech. Dig., P.477 (1991).
3. H.Ohkubo et al., IEDM, Tech. Dig., P.481 (1991).
4. K.Yuzuriha et al., IEDM, Tech. Dig., P.485 (1991).