A 5.9 μm2 super low power SRAM cell using a new phase-shift lithography

Technical Digest - International Electron Devices Meeting

Volumn , Issue , 1990, Pages 477-480

  Yamanaka, T ^a   Hasegawa, N ^a   Tanaka, T ^a   Ishibashi, K ^a   Hashimoto, T ^a   Shimizu, A ^a   Hashimoto, N ^a   Sasaki, K ^a   Nishida, T ^a   Takeda, E ^a  

^a HITACHI LTD   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

DATA STORAGE, SEMICONDUCTOR; LITHOGRAPHY--PHOTOLITHOGRAPHY; SEMICONDUCTING SILICON; TRANSISTORS, FIELD EFFECT;

LOW POWER SRAM; MEMORY CELLS; PHASE-SHIFT LITHOGRAPHY; PMOS TRANSISTORS; POLYSILICON; SRAM;

DATA STORAGE, DIGITAL;

EID: 0025578734     PISSN: 01631918     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (7)