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Volumn 34, Issue 6, 1999, Pages 856-865

Multiple twisted dataline techniques for multigigabit DRAM's

Author keywords

[No Author keywords available]

Indexed keywords

CMOS INTEGRATED CIRCUITS; CROSSTALK; ERRORS; INTERCONNECTION NETWORKS; SIGNAL TO NOISE RATIO; SPURIOUS SIGNAL NOISE; VLSI CIRCUITS;

EID: 0032662749     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/4.766820     Document Type: Article
Times cited : (17)

References (20)
  • 1
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    • Scaling down and reliability problems of gigabit CMOS circuits
    • Jan.
    • W. H. Krautschneider, A. Kohlhase, and H. Terletzki, "Scaling down and reliability problems of gigabit CMOS circuits," Microelectron. Reliab., vol. 37, pp. 19-31, Jan. 1997.
    • (1997) Microelectron. Reliab. , vol.37 , pp. 19-31
    • Krautschneider, W.H.1    Kohlhase, A.2    Terletzki, H.3
  • 3
    • 0026116571 scopus 로고
    • New DRAM pricing trends: The Bi rule
    • Mar.
    • Y. Tarui and T. Tarui, "New DRAM pricing trends: the Bi rule," IEEE Circuits Devices Mag., vol. 7, pp. 44-49, Mar. 1991.
    • (1991) IEEE Circuits Devices Mag. , vol.7 , pp. 44-49
    • Tarui, Y.1    Tarui, T.2
  • 7
    • 0024136904 scopus 로고
    • An experimental 16-Mbit DRAM with transposed data-line structure
    • Feb.
    • M. Aoki, M. Horiguchi, and K. Itoh, "An experimental 16-Mbit DRAM with transposed data-line structure," in ISSCC Dig. Tech. Papers, Feb. 1988, pp. 250-251.
    • (1988) ISSCC Dig. Tech. Papers , pp. 250-251
    • Aoki, M.1    Horiguchi, M.2    Itoh, K.3
  • 12
  • 13
    • 0344613208 scopus 로고
    • 3-D capacitance simulation of DRAM data-line and its application to data-line coupling noise evaluation
    • S. Ikenaga, "3-D capacitance simulation of DRAM data-line and its application to data-line coupling noise evaluation," in Conf. Rec. IEICE Japan. 1987, pp. 164-168.
    • (1987) Conf. Rec. IEICE Japan , pp. 164-168
    • Ikenaga, S.1
  • 14
    • 0030393775 scopus 로고    scopus 로고
    • 3D GIPER: Global interconnect parameter extractor for fullchip global critical path analysis
    • Dec.
    • S. Y. Oh, K. Okasaki, J. Moll, O. S. Nakagawa, K. Rahmat, and N. Chang, "3D GIPER: Global interconnect parameter extractor for fullchip global critical path analysis," in IEDM Tech. Dig., Dec. 1996, pp. 615-618.
    • (1996) IEDM Tech. Dig. , pp. 615-618
    • Oh, S.Y.1    Okasaki, K.2    Moll, J.3    Nakagawa, O.S.4    Rahmat, K.5    Chang, N.6
  • 15
    • 0024175093 scopus 로고
    • A new stacked capacitor DRAM cell characterized by a storage capacitor on a bit-line structure
    • Dec.
    • S. Kimura, "A new stacked capacitor DRAM cell characterized by a storage capacitor on a bit-line structure," in IEDM Tech. Dig., Dec. 1988, pp. 596-599.
    • (1988) IEDM Tech. Dig. , pp. 596-599
    • Kimura, S.1
  • 16
    • 0032028617 scopus 로고    scopus 로고
    • DRAM technology perspective for gigabit era
    • Mar.
    • K. Kim, C. Hwang, and J. Lee, "DRAM technology perspective for gigabit era," IEEE Trans. Electron Devices, vol. 45, pp. 598-608, Mar. 1998.
    • (1998) IEEE Trans. Electron Devices , vol.45 , pp. 598-608
    • Kim, K.1    Hwang, C.2    Lee, J.3


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.