Multiple twisted dataline techniques for multigigabit DRAM's

IEEE Journal of Solid-State Circuits

Volumn 34, Issue 6, 1999, Pages 856-865

  Min, Dong Sun ^a,b,c   Langer, Dietrich W ^{a,d,e,f,g,h,i}  

^a PA 15260   (United States)

^b MOTOROLA INC   (United States)

^c SAMSUNG Electronics   (South Korea)

^d TECHNISCHE UNIVERSITÄT BERLIN   (Germany)

^e AIR FORCE RESEARCH LABORATORY   (United States)

^f HARVARD UNIVERSITY   (United States)

^g ECOLE NORMALE SUPÉRIEURE   (France)

^h MAX PLANCK INSTITUT FÜR FESTKÖRPERFORSCHUNG   (Germany)

ⁱ Indust College of the Armed Forces   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CMOS INTEGRATED CIRCUITS; CROSSTALK; ERRORS; INTERCONNECTION NETWORKS; SIGNAL TO NOISE RATIO; SPURIOUS SIGNAL NOISE; VLSI CIRCUITS;

COUPLING NOISE; TWISTED DATA LINE;

DYNAMIC RANDOM ACCESS STORAGE;

EID: 0032662749     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/4.766820     Document Type: Article

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