1.6GB/s data-rate 1Gb synchronous DRAM with hierarchical square-shaped memory block and distributed bank architecture

Digest of Technical Papers - IEEE International Solid-State Circuits Conference

Volumn 39, Issue , 1996, Pages 376-377

  Nitta, Yasuhiko ^a   Sakashita, Narumi ^a   Shimomura, Ken'ichi ^a   Okuda, Fumihiro ^a   Shimano, Hiroki ^a   Yamakawa, Satoshi ^a   Furukawa, Akihiko ^a   Kise, Koji ^a   Watanabe, Hiroshi ^a   Toyoda, Yoshihiko ^a   Fukada, Tetsuo ^a   Hasegawa, Makiko ^a   Tsukude, Masaki ^a   Arimoto, Kazutami ^a   Baba, Shinji ^a   et al , ^a  

^a Advanced Technology R&D Cent   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

AMPLIFIERS (ELECTRONIC); BANDWIDTH; COMPARATORS (OPTICAL); DATA TRANSFER; DIELECTRIC FILMS; INPUT OUTPUT PROGRAMS; INTEGRATED CIRCUIT TESTING; PHASE LOCKED LOOPS; THREE DIMENSIONAL; TIMING DEVICES; X RAY LITHOGRAPHY;

CHIP SCALE PACKAGE; CLOCK GENERATOR; CURRENT MODE AMPLIFIERS; MICROGRAPHS; PERIPHERAL CIRCUIT; SENSE AMPLIFIERS;

RANDOM ACCESS STORAGE;

EID: 0030082103     PISSN: 01936530     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (4)