A 660 MB/s interface megacell portable circuit in 0.3 μm-0.7 μm CMOS ASIC

IEEE Journal of Solid-State Circuits

Volumn 31, Issue 12, 1996, Pages 1995-2001

  Donnelly, Kevin S ^a,b,c,d,e,f   Chan, Yiu Fai ^{a,b,c,e,g,h,i}   Ho, John T C ^b   Tran, Chanh V ^b   Patel, Samir ^b   Lau, Benedict ^b   Kim, Jun ^b   Chau, Pak Shing ^b   Huang, Charlie ^b   Wei, Jason ^b   Yu, Leung ^b   Tarver, Richard ^b   Kulkarni, Rakhee ^b   Stark, Don ^a,b   Johnson, Mark G ^a,b  

^a IEEE

^b RAMBUS INC   (United States)

^c UNIVERSITY OF CALIFORNIA   (United States)

^d SAN JOSE STATE UNIVERSITY   (United States)

^e Memorex ^*

^f National Semiconductor

^g SANTA CLARA UNIVERSITY   (United States)

^h INTERSIL CORPORATION   (United States)

ⁱ ALTERA CORPORATION   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

AMPLIFIERS (ELECTRONIC); APPLICATION SPECIFIC INTEGRATED CIRCUITS; COMPUTER AIDED DESIGN; DELAY CIRCUITS; DIGITAL CIRCUITS; ELECTRIC CURRENT CONTROL; MICROPROCESSOR CHIPS; TELECOMMUNICATION LINES;

DELAY LOCK LOOPS GENERATED CLOCKS; MEGACELL PORTABLE CIRCUIT;

CMOS INTEGRATED CIRCUITS;

EID: 0030395335     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/4.545823     Document Type: Article

References (7)

1. N. Kushiyama et al., "A 500-MegaBytes/s data-rate 4.5 M DRAM," IEEE J. Solid-State Circuits, vol. 28, pp. 490-498, Dec. 1993.
2. K. Donnelly et al., "A 660 MB/s interface megacell portable circuit in 0.3 μm-0.7 μm CMOS ASIC," in ISSCC Dig. Tech. Papers, Feb. 1996, pp. 290-291.
3. T. Takahashi et al., "A CMOS gate array with 600 Mb/s simultaneous bidirectional I/O circuits," in ISSCC Dig. Tech. Papers, Feb. 1995, pp. 40-41.
4. J. Schutz, "A 3.3 V 0.6 μm BiCMOS superscalar microprocessor," in ISSCC Dig. Tech. Papers, Feb. 1994, pp. 202-203.
5. W. Bowhill et al., "A 300 MHz 64b quad-issue CMOS RISC microprocessor," in ISSCC Dig. Tech. Papers, Feb. 1995, pp. 182-183.
6. T. Lee et al., "A 2.5 V CMOS delay-locked loop for an 18 Mbit, 500 Megabytes/s DRAM," IEEE J. Solid-State Circuits, vol. 29, pp. 1491-1496, Dec. 1994.
7. J. Schutz, "A CMOS 100 MHz Microprocessor," in ISSCC Dig. Tech. Papers, Feb. 1991, pp. 90-91.