0.35 μm CMOS 3-880 MHz PLL N/2 clock multiplier and distribution network with low jitter for microprocessors

Digest of Technical Papers - IEEE International Solid-State Circuits Conference

Volumn 40, Issue , 1997, Pages 330-331

  Young, Ian A ^a   Mar, Monte F ^a   Bhushan, Bharat ^a  

^a INTEL CORPORATION   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ELECTRIC NETWORK TOPOLOGY; FLIP FLOP CIRCUITS; INTEGRATED CIRCUIT LAYOUT; LOGIC GATES; MICROPROCESSOR CHIPS; MULTIPLYING CIRCUITS; PHASE LOCKED LOOPS; SPURIOUS SIGNAL NOISE; TIMING CIRCUITS; VARIABLE FREQUENCY OSCILLATORS;

MICROPROCESSOR CLOCK FREQUENCIES; PHASE LOCKED LOOP (PLL) FREQUENCY GENERATOR;

CMOS INTEGRATED CIRCUITS;

EID: 0031069283     PISSN: 01936530     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (6)