320MHz, 1.5mW at 1.35V CMOS PLL for microprocessor clock generation

Digest of Technical Papers - IEEE International Solid-State Circuits Conference

Volumn 39, Issue , 1996, Pages 132-133

  von Kaenel, Vincent ^a   Aebischer, Daniel ^a   Piguet, Christian ^a   Dijkstra, Evert ^a  

^a CSEM   (Switzerland)

Author keywords

[No Author keywords available]

Indexed keywords

CMOS INTEGRATED CIRCUITS; DETECTOR CIRCUITS; ELECTRIC POWER SUPPLIES TO APPARATUS; FLIP FLOP CIRCUITS; MICROCOMPUTERS; MOS DEVICES; NAND CIRCUITS; POLES AND ZEROS; SIGNAL GENERATORS; SIGNAL TO NOISE RATIO; SPURIOUS SIGNAL NOISE; VARIABLE FREQUENCY OSCILLATORS;

JITTER; LEVEL SHIFTER; PHASE AND FREQUENCY DETECTOR; POWER SUPPLY NOISE REJECTION; POWER SWITCHING NOISE; THRESHOLD VOLTAGES;

PHASE LOCKED LOOPS;

EID: 0030087135     PISSN: 01936530     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (0)