Timing analysis of asynchronous systems using time separation of events

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Volumn 18, Issue 8, 1999, Pages 1061-1076

  Chakraborty, Supratik ^a   Yun, Kenneth Y ^b   Dill, David L ^c  

^a FUJITSU LABORATORIES OF AMERICA   (United States)

^b UNIVERSITY OF CALIFORNIA   (United States)

^c Stanford University   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; COMPUTER AIDED NETWORK ANALYSIS; CONSTRAINT THEORY; DIFFERENTIAL EQUATIONS; MATHEMATICAL MODELS; POLYNOMIALS; TIMING CIRCUITS;

BOUNDED COMPONENT DELAYS; DATAPATH TIMING VERIFICATION; PSEUDOPOLYNOMIAL ALGORITHM; TIME SEPARATION; TIMING ANALYSIS;

ASYNCHRONOUS SEQUENTIAL LOGIC;

EID: 0032631994     PISSN: 02780070     EISSN: None     Source Type: Journal    
DOI: 10.1109/43.775628     Document Type: Article

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