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Volumn 6, Issue 4, 1998, Pages 643-655

The design and verification of a high-performance low-control-overhead asynchronous differential equation solver

Author keywords

Asynchronous design; Average case optimization; Completion sensing; Control overhead; Differential equation solver; Formal verification

Indexed keywords

ASYNCHRONOUS SEQUENTIAL LOGIC; DESIGN; OVERHEAD LINES; TESTING;

EID: 0032303142     PISSN: 10638210     EISSN: None     Source Type: Journal    
DOI: 10.1109/92.736138     Document Type: Article
Times cited : (39)

References (24)
  • 2
    • 0026259615 scopus 로고
    • A zero-overhead self-timed 160ns 54b CMOS divider
    • Nov.
    • T. E. Williams and M. A. Horowitz, "A zero-overhead self-timed 160ns 54b CMOS divider," IEEE J. Solid-State Circuits, vol. 26, pp. 1651-1661, Nov. 1991.
    • (1991) IEEE J. Solid-State Circuits , vol.26 , pp. 1651-1661
    • Williams, T.E.1    Horowitz, M.A.2
  • 3
    • 0003270928 scopus 로고
    • Handshake circuits: An asynchronous architecture for VLSI programming
    • Cambridge, U.K.: Cambridge University Press
    • K. van Berkel, "Handshake circuits: An asynchronous architecture for VLSI programming," in Int. Series Parallel Computation. Cambridge, U.K.: Cambridge University Press, 1993, vol. 5.
    • (1993) Int. Series Parallel Computation , vol.5
    • Van Berkel, K.1
  • 5
    • 0002927123 scopus 로고
    • Programming in VLSI: From communicating processes to delay-insensitive circuits
    • C. A. R. Hoare, Ed. Addison-Wesley, MA: UT Year of Programming Series
    • A. J. Martin, "Programming in VLSI: From communicating processes to delay-insensitive circuits," in Developments in Concurrency and Communication, C. A. R. Hoare, Ed. Addison-Wesley, MA: UT Year of Programming Series, 1990, pp. 1-64.
    • (1990) Developments in Concurrency and Communication , pp. 1-64
    • Martin, A.J.1
  • 8
    • 0031384850 scopus 로고    scopus 로고
    • RTL verification of timed asynchronous and heterogeneous systems using symbolic model checking
    • Dec.
    • V. Vakilotojar and P. A. Beerel, "RTL verification of timed asynchronous and heterogeneous systems using symbolic model checking," Integration, The VLSI J., vol. 24, no. 1, pp. 19-35, Dec. 1997.
    • (1997) Integration, the VLSI J. , vol.24 , Issue.1 , pp. 19-35
    • Vakilotojar, V.1    Beerel, P.A.2
  • 10
    • 0015622069 scopus 로고
    • Some new results on average worst carry
    • May
    • B. E. Briley, "Some new results on average worst carry," IEEE Trans. Comput., vol. C-22, pp. 459-463, May 1973.
    • (1973) IEEE Trans. Comput. , vol.C-22 , pp. 459-463
    • Briley, B.E.1
  • 11
    • 0011781711 scopus 로고    scopus 로고
    • A CMOS VLSI implementation of an asynchronous ALU
    • Asynchronous Design Methodologies, S. Furber and M. Edwards, Eds., New York: Elsevier Science
    • J. D. Garside, "A CMOS VLSI implementation of an asynchronous ALU," in Asynchronous Design Methodologies, S. Furber and M. Edwards, Eds., in IFIP Transactions. New York: Elsevier Science, vol. A-28, pp. 181-207.
    • IFIP Transactions , vol.A-28 , pp. 181-207
    • Garside, J.D.1
  • 12
    • 0030110561 scopus 로고    scopus 로고
    • An evaluation of asynchronous addition
    • Mar.
    • D. J. Kinnement, "An evaluation of asynchronous addition," IEEE Trans. VLSI Syst., vol. 4, pp. 137-140, Mar. 1996.
    • (1996) IEEE Trans. VLSI Syst. , vol.4 , pp. 137-140
    • Kinnement, D.J.1
  • 15
    • 0029708262 scopus 로고    scopus 로고
    • A high throughput 16 by 16 bit multiplier for DSP cores
    • May
    • C. Lemonds, "A high throughput 16 by 16 bit multiplier for DSP cores," in IEEE Int. Symp. Circuits Syst. (ISCAS), May 1996, pp. 477-480.
    • (1996) IEEE Int. Symp. Circuits Syst. (ISCAS) , pp. 477-480
    • Lemonds, C.1
  • 17
    • 0029727772 scopus 로고    scopus 로고
    • Automatic synthesis of extended burst-mode circuits using generalized C-elements
    • Sept.
    • K. Y. Yun, "Automatic synthesis of extended burst-mode circuits using generalized C-elements," in Proc. European Design Automation Conf. (EURO-DAC), Sept. 1996, pp. 290-295.
    • (1996) Proc. European Design Automation Conf. (EURO-DAC) , pp. 290-295
    • Yun, K.Y.1
  • 21
    • 24344458811 scopus 로고
    • Advances in asynchronous circuit theory; Part II: Bounded inertial delay models, MOS circuit design techniques
    • Feb.
    • J. A. Brzozowski and C.-J. H. Seger, "Advances in asynchronous circuit theory; Part II: Bounded inertial delay models, MOS circuit design techniques," Bull. EATCS, no. 43, pp. 199-263, Feb. 1991.
    • (1991) Bull. EATCS , Issue.43 , pp. 199-263
    • Brzozowski, J.A.1    Seger, C.-J.H.2
  • 24
    • 0031629742 scopus 로고    scopus 로고
    • Practical timing analysis of asynchronous circuits using time separation of events
    • May
    • S. Chakraborty, K. Y. Yun, and D. L. Dill, "Practical timing analysis of asynchronous circuits using time separation of events," in Proc. Custom Integrated Circuits Conf., May 1998, pp. 455-458.
    • (1998) Proc. Custom Integrated Circuits Conf. , pp. 455-458
    • Chakraborty, S.1    Yun, K.Y.2    Dill, D.L.3


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.