On deducing timing constraints in the verification of interfaces

Formal Methods in System Design

Volumn 12, Issue 3, 1998, Pages 223-239

  Mavaddat, F ^a   Gahlinger, T ^b  

^a UNIVERSITY OF WATERLOO   (Canada)

^b Tony Gahlinger and Associates Inc   (Canada)

Author keywords

Digital design verification; Interfacing; Timing diagrams; Timing verification

Indexed keywords

DIGITAL DESIGN VERIFICATION; INTERFACING; TIMING DIAGRAMS; TIMING VERIFICATION;

DIGITAL SIGNAL PROCESSING; INTERCONNECTION NETWORKS; INTERFACES (COMPUTER); SYSTEMS ANALYSIS; THEOREM PROVING; WAVEFORM ANALYSIS; CONSTRAINT THEORY; MATHEMATICAL MODELS;

DELAY CIRCUITS; INTERFACES (COMPUTER);

DIGITAL DESIGN VERIFICATION; SEPARATION BOUNDS; WAVEFORM TIMING SPECIFICATIONS;

EID: 0032047615     PISSN: 09259856     EISSN: None     Source Type: Journal    
DOI: 10.1023/A:1008626616397     Document Type: Article

References (16)

1. J. Benkoski, E. Vanden Meersch, L. Claesen, and H. De Man, "Efficient algorithms for solving the false path problem in timing verification," IEEE International Conference on Computer-Aided Design. ICCAD-87, Santa Clara, California, pp. 44-47, Nov. 1987.
2. G. Borriello, "A new interface specification methodology and its application to transducer synthesis," Ph.D. Thesis, Computer Science Division, EECS, University of California, Berkeley, May 1988.
3. D. Brand and V. Iyengar, "Timing analysis using functional relationships," IEEE International Conference on Computer-Aided Design. ICCAD-86, Santa Clara, California, pp. 125-129, Nov. 1986.
4. J.A. Brzozowski, T. Gahlinger, and F. Mavaddat, "Consistency and satisfiability of waveform timing specifications," Networks, Vol. 21, pp. 91-107, 1991.
5. E. Cerny and K. Khordoc, "Interface specification with conjunctive timing constraints: Realizability and compatibility," Second AMAST Workshop on Real-Time Systems, Bordeaux, France, June 1995.
6. T. Gahlinger, "Coherence and satisfiability of waveform timing specifications," Ph.D. Thesis, Department of Computer Science, University of Waterloo, Waterloo, 1989.
7. R.B. Hitchcock, "Timing verification and the timing analysis program," 19th Design Automation Conference, IEEE, pp. 594-604, 1982.
8. T.I. Kirkpatrick and N.R. Clark, "PERT as an aid to logic design," IBM Journal of Research and Development, pp. 135-141, March 1966.
9. K. McMillan and D.L. Dill, "Algorithms for interface timing verification," 1992 IEEE International Conference on Computer Design: VLSI in Computers and Processors, IEEE Computer Society, 1992.
10. P. Rony, "Interfacing fundamentals: Timing diagram conventions," Computer Design, pp. 152-153, Jan. 1980.
11. A. Ruehli and D.L. Ostapko, "VLSI Circuit analysis, timing verification and optimization," in Fichter and Morf (Eds.), VLSI CAD Tools and Applications, Kluwer Publ., Boston, pp. 129-146, 1987.
12. J. Springer, "Making sense out of delay specs in semiconductor memories," Electronics, pp. 82-88, Oct. 1971.
13. Toshiba, Inc., MOS Memory Products Databook 1983-1984, 1984.
14. P. Vanbekbergen, G. Goossens, and H. De Man, "Specification and analysis of timing constraints in signal transition graphs," European DAC, 1992.
15. C. Wiatrowski and C. House, Logic Circuits and Microcomputer Systems, McGraw-Hill, 1980.
16. Zilog, Inc., 1982/1983 Data Book, 1983.