Efficient algorithms for interface timing verification

Formal Methods in System Design

Volumn 12, Issue 3, 1998, Pages 241-265

  Yen, Ti Yen ^a   Ishii, Alex ^b   Casavant, Al ^b   Wolf, Wayne ^a  

^a PRINCETON UNIVERSITY   (United States)

^b NEC LABORATORIES AMERICA   (United States)

Author keywords

Linear and max constraints; Microprocessor bus; Timing verification

Indexed keywords

LINEAR AND MAX CONSTRAINTS; MICROPROCESSOR BUS; TIMING VERIFICATION; VERIFICATION ALGORITHMS;

ALGORITHMS; BUSBARS; INTERFACES (COMPUTER); LARGE SCALE SYSTEMS; MICROPROCESSOR CHIPS; PROBLEM SOLVING; COMPUTATIONAL COMPLEXITY; COMPUTATIONAL METHODS; CONSTRAINT THEORY; CONVERGENCE OF NUMERICAL METHODS;

DELAY CIRCUITS; INTERFACES (COMPUTER);

INTERFACE TIMING VERIFICATION; MICROPROCESSOR BUS;

EID: 0032047061     PISSN: 09259856     EISSN: None     Source Type: Journal    
DOI: 10.1023/A:1008680300467     Document Type: Article

References (23)

1. T. Amon, H. Hulgaard, S.M. Burns, and G. Borriello, "An algorithm for exact bounds on the time separation of events in concurrent systems," in Proceedings of IEEE International Conference on Computer Design, pp. 166-173, 1993.
2. G. Borriello and R. Katz, "Synthesis and optimization of interface transducer logic," in Proceedings of IEEE International Conference on Computer-Aided Design, 1987.
3. J.A. Brzozowski, T. Gahlinger, and F. Mavaddat, "Consistency and satisfiability of waveform timing specification," Networks, pp. 91-107, Jan. 1991.
4. T. Burks and K. Sakallah, "Min-max linear programming and the timing analysis of digital circuits," in Proceedings of IEEE International Conference on Computer-Aided Design, pp. 152-155, 1993.
5. P. Chou, E.A. Walkup, and G. Borriello, "Scheduling for reactive real-time systems," IEEE MICRO, Vol. 14, No. 4, pp. 37-47, Aug. 1994.
6. T.H. Cormen, C.E. Leiserson, and R.L. Rivest, Introduction to Algorithms. McGraw-Hill, 1990.
7. A.J. Daga and W.P. Birmingham, "VITCh: A methodology for the timing verification of board-level circuits," in Proceedings of TAU Workshop, 1993.
8. T. Gahlinger, "Coherence and satisfiability of waveform timing specification," Ph.D. thesis, University of Waterloo, May 1990.
9. Integrated Device Technology, Inc., Logic Data Book, 1990.
10. Intel Corporation, Microsystem Components Handbook, 1986.
11. Intel Corporation, Microprocessors, 1990.
12. Intel Corporation, Memory, 1990.
13. D. Ku and G. de Micheli, "Relative scheduling under timing constraints," IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems, Vol. 11, No. 6, pp. 696-717, June 1992.
14. L. Lavagno and A. Sangiovanni-Vincentelli, "Linear programming for optimum hazard elimination in asynchronous circuits," in Proceedings of IEEE International Conference on Computer Design, 1992.
15. Y.-Z. Liao and C.K. Wong, "An algorithm to compact a VLSI symbolic layout with mixed constraints," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. CAD-2, No. 2, pp. 62-69, April 1983.
16. K. McMillan and D. Dill, "Algorithms for interface timing verification," in Proceedings of IEEE International Conference on Computer Design, pp. 48-51, 1992.
17. C. Myers and T.H.Y. Meng, "Synthesis of timed asynchronous circuits," in Proceedings of IEEE International Conference on Computer Design, pp. 279-284, 1992.
18. K.A. Sakallah, T.N. Mudge, and O.A. Olukotun, "Timing verification and optimal clocking of synchronous digital circuits," in Proceedings of IEEE International Conference on Computer-Aided Design, 1990.
19. P. Vanbekbergen, G. Goossens, and H. de Man, "Specification and analysis of timing constraints in signal transition graphs," in Proceedings of the European Conference on Design Automation, pp. 302-306, 1992.
20. E.A. Walkup, "Optimization of linear max-plus systems with application to timing analysis," Ph.D. thesis, University of Washington, 1995.
21. E.A. Walkup and G. Borriello, "Interface timing verification with application to synthesis," in Proceedings of Design Automation Conference, pp. 106-112, 1994.
22. W.H. Wolf and A.E. Dunlop, "Symbolic layout and compaction" in B.T. Preas and M.J. Lorenzetti (Eds.), Physical Design Automation of VLSI Systems, Benjamin-Cummings, Chap. 6, pp. 211-281, 1988.
23. Ti-Yen Yen and W. Wolf, "Performance estimation for real-time distributed embedded systems," in Proceedings of IEEE International Conference on Computer Design, pp. 64-69, 1995.