-
1
-
-
33749786155
-
-
1992.
-
D.D. Gajski, N. Dutt, A. Wu, and S. Lin, High-Level Synthesis: Introduction to Chip and System Design. Boston, MA: Kluwer Academic, 1992.
-
N. Dutt, A. Wu, and S. Lin, High-Level Synthesis: Introduction to Chip and System Design. Boston, MA: Kluwer Academic
-
-
Gajski, D.D.1
-
2
-
-
0026997848
-
-
182-187.
-
W. Wolf, A. Takach, C. Huang, and R. Mano, "The Princeton university behavioral synthesis system," in Proc. Design Automation Conf., June 1992, pp. 182-187.
-
A. Takach, C. Huang, and R. Mano, "The Princeton University Behavioral Synthesis System," in Proc. Design Automation Conf., June 1992, Pp.
-
-
Wolf, W.1
-
3
-
-
0026883812
-
-
1992.
-
D. Ku and G. De Micheli, "Relative scheduling under timing constraints," IEEE Trans. Computer-Aided Design, vol. 11, pp. 696-718, June 1992.
-
And G. De Micheli, "Relative Scheduling under Timing Constraints," IEEE Trans. Computer-Aided Design, Vol. 11, Pp. 696-718, June
-
-
Ku, D.1
-
4
-
-
0025791177
-
-
1991.
-
R. Camposano, "Path-based scheduling for synthesis," IEEE Trans. Computer-Aided Design, vol. 10, pp. 85-93, Jan. 1991.
-
"Path-based Scheduling for Synthesis," IEEE Trans. Computer-Aided Design, Vol. 10, Pp. 85-93, Jan.
-
-
Camposano, R.1
-
5
-
-
0028608174
-
-
491-196.
-
S. Bhattacharya, S. Dey, and F. Brglez, "Performance analysis and optimization of schedules for conditional and loop-intensive specifications," in Proc. Design Automation Conf., June 1994, pp. 491-196.
-
S. Dey, and F. Brglez, "Performance Analysis and Optimization of Schedules for Conditional and Loop-intensive Specifications," in Proc. Design Automation Conf., June 1994, Pp.
-
-
Bhattacharya, S.1
-
6
-
-
0031101541
-
-
1997.
-
R. Bergamaschi, S. Raje, I. Nair, and L. Trevillyan, "Control-flow versus data-flow scheduling: Combining both approaches in an adaptive scheduling system," IEEE Trans. Very Large Scale Integration Syst., vol. 5, pp. 82-100, Mar. 1997.
-
S. Raje, I. Nair, and L. Trevillyan, "Control-flow Versus Data-flow Scheduling: Combining both Approaches in an Adaptive Scheduling System," IEEE Trans. Very Large Scale Integration Syst., Vol. 5, Pp. 82-100, Mar.
-
-
Bergamaschi, R.1
-
7
-
-
0028591704
-
-
542-546.
-
Y. Fann, M. Rim, and R. Jain, "Global scheduling for high-level synthesis applications," in Proc. Design Automation Conf., June 1994, pp. 542-546.
-
M. Rim, and R. Jain, "Global Scheduling for High-level Synthesis Applications," in Proc. Design Automation Conf., June 1994, Pp.
-
-
Fann, Y.1
-
8
-
-
0028426397
-
-
1994.
-
S. Amellal and B. Kaminska, "Functional synthesis of digital systems with TASS," IEEE Trans. Computer-Aided Design, vol. 13, pp. 537-552, May 1994.
-
And B. Kaminska, "Functional Synthesis of Digital Systems with TASS," IEEE Trans. Computer-Aided Design, Vol. 13, Pp. 537-552, May
-
-
Amellal, S.1
-
9
-
-
0028413092
-
-
1994.
-
T. Kim, N. Yonezawa, J.W.S. Liu, and C.L. Liu, "A scheduling algorithm for conditional resource sharing-A hierarchical reduction approach," IEEE Trans. Computer-Aided Design, vol. 13, pp. 425-138, Apr. 1994.
-
N. Yonezawa, J.W.S. Liu, and C.L. Liu, "A Scheduling Algorithm for Conditional Resource Sharing-A Hierarchical Reduction Approach," IEEE Trans. Computer-Aided Design, Vol. 13, Pp. 425-138, Apr.
-
-
Kim, T.1
-
11
-
-
0029480372
-
-
1995.
-
A. Aiken, A. Nikolau, and S. Novack, "Resource-constrained software pipelining," IEEE Trans. Parallel Distrib. Syst., vol. 6, pp. 1248-1269, Dec. 1995.
-
A. Nikolau, and S. Novack, "Resource-constrained Software Pipelining," IEEE Trans. Parallel Distrib. Syst., Vol. 6, Pp. 1248-1269, Dec.
-
-
Aiken, A.1
-
13
-
-
0002017307
-
-
1993.
-
B.R. Rau and J.A. Fisher, "Instruction-level parallel processing: History, overview, and perspective," J. Supercomputing, vol. 7, pp. 9-50, July 1993.
-
And J.A. Fisher, "Instruction-level Parallel Processing: History, Overview, and Perspective," J. Supercomputing, Vol. 7, Pp. 9-50, July
-
-
Rau, B.R.1
-
14
-
-
0024883468
-
-
826-831.
-
G. Goossens, J. Vanderwalle, and H. De Man, "Loop optimization in register-transfer scheduling for DSP systems," in Proc. Design Automation Conf., June 1989, pp. 826-831.
-
J. Vanderwalle, and H. De Man, "Loop Optimization in Register-transfer Scheduling for DSP Systems," in Proc. Design Automation Conf., June 1989, Pp.
-
-
Goossens, G.1
-
15
-
-
0027660749
-
-
1993.
-
C.-T. Hwang, Y.-C Hsu, and Y.-L. Lin, "PLS: Scheduler for pipeline synthesis," IEEE Trans. Computer-Aided Design, vol. 12, pp. 1279-1286, Sept. 1993.
-
Y.-C Hsu, and Y.-L. Lin, "PLS: Scheduler for Pipeline Synthesis," IEEE Trans. Computer-Aided Design, Vol. 12, Pp. 1279-1286, Sept.
-
-
Hwang, C.-T.1
-
17
-
-
0029267885
-
-
1995.
-
C. Wang and K.K. Parhi, "High-level DSP synthesis using concurrent transformations, scheduling, and allocation," IEEE Trans. ComputerAided Design, vol. 14, pp. 274-295, Mar. 1995.
-
And K.K. Parhi, "High-level DSP Synthesis Using Concurrent Transformations, Scheduling, and Allocation," IEEE Trans. ComputerAided Design, Vol. 14, Pp. 274-295, Mar.
-
-
Wang, C.1
-
22
-
-
0031641699
-
-
108-113.
-
G. Lakshminarayana, A. Raghunathan, and N.K. Jha, "Incorporating speculative execution into scheduling for control-flow intensive behaviors," in Proc. Design Automation Conf., June 1998, pp. 108-113.
-
A. Raghunathan, and N.K. Jha, "Incorporating Speculative Execution into Scheduling for Control-flow Intensive Behaviors," in Proc. Design Automation Conf., June 1998, Pp.
-
-
Lakshminarayana, G.1
-
23
-
-
33749795418
-
-
1997.
-
G. Lakshminarayana, K.S. Khouri, and N.K. Jha, "Wavesched: A novel scheduling algorithm for control-flow intensive behaviors," Princeton Univ., Princeton, NJ, Tech. Rep. CE-J97-001, 1997.
-
K.S. Khouri, and N.K. Jha, "Wavesched: a Novel Scheduling Algorithm for Control-flow Intensive Behaviors," Princeton Univ., Princeton, NJ, Tech. Rep. CE-J97-001
-
-
Lakshminarayana, G.1
-
26
-
-
0030397950
-
-
322-329.
-
F.F. Hsu, E.M. Rudnick, and J.H. Patel, "Enhancing high level control-flow for improved testability," in Proc. Int. Conf. ComputerAided Design, Nov. 1996, pp. 322-329.
-
E.M. Rudnick, and J.H. Patel, "Enhancing High Level Control-flow for Improved Testability," in Proc. Int. Conf. ComputerAided Design, Nov. 1996, Pp.
-
-
Hsu, F.F.1
-
27
-
-
85050214309
-
-
461-66.
-
A.C. Parker, J.T. Pizzaro, and M. Mlinar, "MAHA: A program for datapath synthesis," in Proc. Design Automation Conf., June 1986, pp. 461-66.
-
J.T. Pizzaro, and M. Mlinar, "MAHA: a Program for Datapath Synthesis," in Proc. Design Automation Conf., June 1986, Pp.
-
-
Parker, A.C.1
-
28
-
-
0027002268
-
-
300-303.
-
A.P. Chandrakasan, M. Potkonjak, J. Rabaey, and R.W. Brodersen, "HYPER-LP: A system for power minimization using architectural transformations," in Proc. Int. Conf. Computer-Aided Design, Nov. 1992, pp. 300-303.
-
M. Potkonjak, J. Rabaey, and R.W. Brodersen, "HYPER-LP: a System for Power Minimization Using Architectural Transformations," in Proc. Int. Conf. Computer-Aided Design, Nov. 1992, Pp.
-
-
Chandrakasan, A.P.1
-
30
-
-
0024682923
-
-
1989.
-
P.G. Paulin and J.P. Knight, "Force-directed scheduling for behavioral synthesis of ASIC's," IEEE Trans. Computer-Aided Design, vol. 8, pp. 661-679, June 1989.
-
And J.P. Knight, "Force-directed Scheduling for Behavioral Synthesis of ASIC's," IEEE Trans. Computer-Aided Design, Vol. 8, Pp. 661-679, June
-
-
Paulin, P.G.1
|