PLS: A Scheduler for Pipeline Synthesis

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Volumn 12, Issue 9, 1993, Pages 1279-1286

  Hwang, Cheng Tsung ^a   Hsu, Yu Chin ^a   Lin, Youn Long ^b  

^a UNIVERSITY OF CALIFORNIA   (United States)

^b NATIONAL TSING HUA UNIVERSITY   (Taiwan)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; DIGITAL SIGNAL PROCESSING; OPTIMIZATION; SCHEDULING;

PIPELINE SYNTHESIS; SCHEDULER;

PIPELINE PROCESSING SYSTEMS;

EID: 0027660749     PISSN: 02780070     EISSN: 19374151     Source Type: Journal    
DOI: 10.1109/43.240075     Document Type: Article

References (16)

1. M. C. McFarland, A. C. Parker, and R. Camposano, “The high-level synthesis of digital system,” in Proc. IEEE, vol. 78, pp. 301–318, Feb. 1990.
2. J. L. Hennessy and D. A. Patterson, Computer Architecture: A Quantitative Approach. Margan Kaufmann, 1990, pp. 327.
3. N. Park and A. C. Parker, “Sehwa: A software package for synthesis of pipelines from behavioral specifications,” IEEE Trans. Computer-Aided Design, vol. 7, pp. 356–370, Mar. 1988.
4. P. G. Paulin and J. P. Knight, “Force-directed scheduling for the behavioral synthesis of ASIC’s,” IEEE Trans. Computer-Aided Design, vol. 8, pp. 661–679, June 1989.
5. Ki Soo Hwang, Albert E. Casavant, Ching-Tand Chang, and Manuel A. d’Abreu, “Scheduling and hardware sharing in pipelined data paths,” Proc. ICCAD-89, pp. 24–27, Nov. 1989.
6. E. M. Girczyc, “Loop winding—A data flow approach to functional pipelining,” Proc. IEEE ISCAS, pp. 382–385, May 1987.
7. R. Potasman, J. Lis, A. Aiken, and A. Nicolau, “Percolation based synthesis,” in Proc. 27th Design Automation Conf., pp. 444–449, 1990.
8. A. Aiken and A. Nicolau, “Optimal loop parallelization,” in Proc. 1988 ACM SIGPLAN Conf. on Prog. Lang. Design and Implementation, 1988.
9. B. S. Haroun and M. I. Elmasry, “Architectural synthesis for DSP silicon compiler,” IEEE Trans. Computer-Aided Design, vol. 8, pp. 431–447, Apr. 1989.
10. G. Goossens, J. Rabaey, J. Vandewalle, and H. De Man, “An efficient micro-code compiler for applications specific DSP processors,” IEEE Trans. Computer-Aided Design, vol. 9, pp. 925–937, June 1990.
11. M. S. Lam, “A systolic array optimizing compiler,” Ph.D. dissertations, Carnegie Mellon Univ., 1989.
12. Cytron, R., “Compiler-time scheduling optimization for asynchronous machines,” Ph.D. dissertation, Univ. Illinois at Urbana-Champaign, 1984.
13. C. T. Hwang, Y. C. Hsu, and Y. L. Lin “Optimum and heuristic data path scheduling under resource constraints,” in Proc. 27th Design Automation Conf., pp. 65–70, July 1990.
14. F. S. Tsai and Y. C. Hsu, “Datapath construction and refinement,” in Proc. ICCAD-90, pp. 308–311, 1990.
15. S. Y. Kung, H. J. Whitehouse, and T. Kailath, VLSI and Modern Signal Processing. Englewood Cliffs, NJ: Prentice Hall, pp. 258–264, 1985.
16. D. J. Mallon and P. B. Denyer, “A new approach to pipeline optimisation,” in Proc. European Design Automation Conf., Mar. 1990.