Functional Synthesis of Digital Systems with TASS

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Volumn 13, Issue 5, 1994, Pages 537-552

  Amellal, Said ^a   Bozena, Kaminska ^a  

^a ÉCOLE POLYTECHNIQUE DE MONTRÉAL   (Canada)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER AIDED DESIGN; MICROPROCESSOR CHIPS;

DATA PATH; FUNCTIONAL SYNTHESIS; SEARCH SYNTHESIS;

DIGITAL INTEGRATED CIRCUITS;

EID: 0028426397     PISSN: 02780070     EISSN: 19374151     Source Type: Journal    
DOI: 10.1109/43.277628     Document Type: Article

References (38)

1. G. G. de Jong, “Data flow graph: System specification with the most unrestricted semantics,” in Proc. European Design Autom. Conf, 1991, 401–405.
2. J. T. J. Van Eijndhoven and L. Stok, “A data flow graph exchange standard,” in Proc. European Design Autom. Conf., 1992, p. 193–199.
3. T. Krol, J. V. Meerbergen, C. Niessen, W. Smits, and J. Huisken, “The Sprite input language, an intermediate format for high-level synthesis,” in Proc. European Design Autom. Conf., 1991, pp. 186–192.
4. M. Rim and R. Jain, “Representing conditional branches for high-level synthesis applications,” in Proc. 29th ACM/IEEE Design Autom. Conf., 1992, pp. 106–111.
5. N. Park and A. C. Parker, “Sehwa: A software package for synthesis of pipelines from behavioral specifications,” IEEE Trans. Computer-Aided Design, pp. 356–370, Mar. 1988.
6. K. Wakabayashi and T. Yoshimura, “A resource sharing and control synthesis method for conditional branches,” in Proc. Int. Conf. Computer-Aided Design, 1989.
7. A. C. Parker, J. Pizzaro, and M. J. Mlinar, “MAHA: A program for data path synthesis,” in Proc. Int. Conf. Computer-Aided Design, 1988, pp. 52–55.
8. R. Composano, “Path-based scheduling for synthesis,” IEEE Trans. Computer-Aided Design, vol. 10, pp. 85–93, Jan. 1991.
9. K. Wakabayashi and H. Tanaka, “Global scheduling independent of control dependencies based on conditions vectors,” in Proc. 29th ACM/IEEE Design Autom. Conf., 1992, pp. 112–115.
10. T. Kim, J. S. Liu, and C. L. Liu, “Scheduling algorithm for conditional resource sharing,” in Proc. Int. Conf. Computer-Aided Design, 1991, pp. 84–87.
11. F. Glover, “Tabu Search, Part I,” ORSA J. Computing, pp. 190–206, 1989.
12. F. Glover, “Tabu Search, Part II,” ORSA J. Computing, pp. 4-32, 1989.
13. F. Glover, “Tabu Search: A tutorial” Center for Applied Artificial UIntellegence, Univ. of Colorado, Boulder, Feb 1990.
14. P. G. Paulin and J. P. Knight, “Algorithms for high-level synthesis,” IEEE Design & Test, pp. 18–31, Oct. 1989.
15. H. Shin and N. S. Woo, “A cost function based optimization technique for scheduling in data path synthesis,” in Proc. Int. Conf. Computer-Aided Aided Design, 1989, pp. 424–427.
16. C. A. Papachriston and H. Konuk, “A linear-driven scheduling and allocation method followed by interconnect optimization algorithm,” in Proc. 27th ACM/IEEE Design Autom. Conf., 1990, pp. 77–83.
17. J. Lee, Y. Hsu, and Y. Lin, “A new integer linear programming formulation for the scheduling problem in data path synthesis,” in Proc. Int. Conf. Computer-Aided Design, 1989, pp. 20–23.
18. C. T. Hwang, J. H. Lee, and Y. C. Hsu, “A formal approach to the scheduling problem in high-level synthesis,” IEEE Trans. Computer-Aided Aided Design, vol. 10, pp. 464–475, Apr. 1991.
19. P. Dewilde, E. Deprettere, and R. Nouta, “Parallel and pipelined VLSI implementation of signal processing algorithms,” VLSI and Modern Signal Processing, S. Y. King, H. J. Whitehouse, and T. Kailath, eds. Englewood Cliffs, NJ: Prentice-Hall, 1985, pp. 257–275.
20. S. Devadas and R. Newton, “Algorithms for hardware allocation in data path synthesis,” IEEE Trans, Computer-Aided Design, vol. CAD-7, pp. 768–781, July 1989.
21. P. G. Paulin and J. P. Knight, “Force-directed scheduling for the behavioral synthesis of ASIC’s,” IEEE Trans. Computer-Aided Design, vol. 8, pp. 661–679, June 1989.
22. L. Ramachandran and D. D. Gajski, “An algorithm for component selection in performance optimized scheduling,” in Proc. Int. Conf. Computer-Aided Design, 1991, pp. 92–95.
23. C.J. Tseng and D. P. Siewiorek, “FACET: A procedure for the automated synthesis of digital systems,” in Proc. 20th ACM/IEEE Design Autom. Conf., 1983, pp. 490–496.
24. B. M. Pangrle and D. D. Gajski, “Design tools for intelligent silicon compilation,” IEEE Trans. Computer-Aided Design, vol. CAD-6. pp. 1098–1112, Nov. 1987.
25. C.J. Tseng, and D. P. Siewiorek, “Automated synthesis of data paths in digital systems,” IEEE Trans. Computer-Aided Design, vol. CAD-5. pp. 379–395, July 1986.
26. M. Jamoussi, B. Kaminska. “Controllability and observability measures for functional-level testability evaluation.” in Proc. 11th VLSI Test Symp., 1993, pp. 154–157.
27. S. Amellal and B. Kaminska, “Scheduling algorithm in data path synthesis using the Tabu Search technique,” in Proc. European Design Autom. Conf., Paris, France, Feb. 1993, pp. 398–402.
28. J. Roy, and R. Vemuri, “Appropriate usage of VHDL: The synthesis Point of Views,” Tech. Memo, Univ. of Cincinnati. May 1990.
29. H. Oudghiri and B. Kaminska, “Global weighted scheduling and allocation algorithms,” in Proc. European Design Autom. Conf., 1992. pp. 491-495.
30. S. Amellal and B. Kaminska, “Scheduling of control and data flow graph,” in Proc. Int. Symp. on Computers and Systems. Chicago. pp. 1666–1669, May 1993.
31. D. Gajski, N. Dutt, A. Wu, and S. Lin, High-Level Synthesis Introduction to Chip and System Design. Boston, MA: Kluwer Academic. 1992.
32. L. Hafer and A. Parker, “A formal method for the specification. analysis, and design of register-transfer level digital logic,” IEEE Trans. Computer-Aided Design, Jan. 1983.
33. J. J. Granacki, et al., “The ADAM advanced design automation system: Overview, planner, and natural language interface,” in Proc. 22th Design Autom. Conf., 1985.
34. R. A. Walker and D. E. Thomas. “Behavioral transformation for algorithmic level IC design,” IEEE Trans. Computer-Aided Design. Oct. 1989.
35. J. S. Lis and D. D. Gajski, “Synthesis from VHDL,” in Proc. IEEE ICCD. 1988, pp. 378–381.
36. B. M. Pangrle, “A Behavioral Compiler for Intelligent Silicon Compiler,” Univ. of Illinois at Urbana, Champaign, 1987.
37. A. L. Davis and R. M. Keller, “Data flow program graphs,” IEEE Trans. Computers, 1982.
38. M. Jamoussi, B. Kaminska, and D. Mukhedkar, “A New testability measure: A concept for data flow testability evaluation,” in Proc. 5th Int. Conf. VLSI Design, Jan. 1992, pp. 239–244.