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Volumn 5, Issue 1, 1997, Pages 82-100

Control-flow versus data-flow-based scheduling: Combining both approaches in an adaptive scheduling system

Author keywords

Control flow graph; Data flow graph; High level synthesis; Path based scheduling

Indexed keywords

ADAPTIVE SYSTEMS; ALGORITHMS; COMPUTATIONAL COMPLEXITY; GRAPH THEORY; OPTIMIZATION; ROBUSTNESS (CONTROL SYSTEMS); SCHEDULING;

EID: 0031101541     PISSN: 10638210     EISSN: None     Source Type: Journal    
DOI: 10.1109/92.555989     Document Type: Review
Times cited : (39)

References (16)
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    • Camposano, R.1
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    • Bergamaschi, R.A.1    Camposano, R.2    Payer, M.3
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  • 10
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    • A graph-based silicon compiler for concurrent VLSI systems
    • Brussels, Belgium, Apr.
    • R. A. Bergamaschi and D. J. Allerton, "A graph-based silicon compiler for concurrent VLSI systems," in Proc. IEEE CompEuro Conf., Brussels, Belgium, Apr. 1988, pp. 36-47.
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    • M. C. McFarland and T. J. Kowalski, "Incorporating bottom-up design into hardware synthesis," IEEE Trans. Computer-Aided Design, vol. 9, pp. 938-950, Sept. 1990.
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* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.