The effects of interlayer dielectric deposition and processing on the reliability of N-channel transistors

Solid-State Electronics

Volumn 42, Issue 11, 1998, Pages 2031-2037

  Trabzon, L ^a   Awadelkarim, O O ^a   Werking, J ^b  

^a PENNSYLVANIA STATE UNIVERSITY   (United States)

^b SEMATECH   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

DEGRADATION; DIELECTRIC MATERIALS; ELECTRIC BREAKDOWN OF SOLIDS; ELECTRIC CHARGE; ELECTRIC NETWORK ANALYSIS; ELECTRIC NETWORK PARAMETERS; GATES (TRANSISTOR); PLASMA ENHANCED CHEMICAL VAPOR DEPOSITION; PLASMA ETCHING; RELIABILITY; SEMICONDUCTING SILICON COMPOUNDS; STRESS ANALYSIS;

FLUORINATED SILICON OXIDES; FOWLER-NORDHEIM (FN) STRESS RELIABILITY; INTERLAYER DIELECTRIC (ILD) DEPOSITION;

MOSFET DEVICES;

EID: 0032208659     PISSN: 00381101     EISSN: None     Source Type: Journal    
DOI: 10.1016/S0038-1101(98)00175-0     Document Type: Article

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