On the effect of floorplanning on the yield of large area integrated circuits

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Volumn 5, Issue 1, 1997, Pages 3-14

  Koren, Zahava ^a   Koren, Israel ^b,c  

^a UNIVERSITY OF MASSACHUSETTS   (United States)

^b University of Massachusetts at Amherst   (United States)

^c IEEE

Author keywords

Clustering; Defects; Fault tolerant IC's; Floorplan; Large area IC's; Yield

Indexed keywords

CALCULATIONS; FAILURE ANALYSIS; FAULT TOLERANT COMPUTER SYSTEMS; MATHEMATICAL MODELS; PROBABILITY; STATISTICAL METHODS; VLSI CIRCUITS;

FLOORPLAN STRUCTURES; LARGE AREA INTEGRATED CIRCUITS; NEGATIVE BINOMIAL DISTRIBUTION;

INTEGRATED CIRCUIT LAYOUT;

EID: 0031098217     PISSN: 10638210     EISSN: None     Source Type: Journal    
DOI: 10.1109/92.555982     Document Type: Article

References (15)

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