Yield enhanced routing for high-performance VLSI designs

Proceedings of SPIE - The International Society for Optical Engineering

Volumn 3216, Issue , 1997, Pages 51-60

  Venkataraman, A ^a   Chen, Howard H ^b   Koren, I ^a  

^a University of Massachusetts   (United States)

^b IBM RESEARCH   (United States)

Author keywords

Channel routing; Critical area reduction; Crosstalk noise; Design for manufacturability; Yield enhancement techniques

Indexed keywords

COMPUTER AIDED DESIGN; CROSSTALK; DESIGN; FAILURE ANALYSIS; INTEGRATED CIRCUITS; MACHINE DESIGN; QUALITY ASSURANCE; RELIABILITY; RELIABILITY ANALYSIS; SAFETY FACTOR;

CHANNEL ROUTING; CRITICAL AREA REDUCTION; CROSSTALK NOISE; DESIGN FOR MANUFACTURABILITY; YIELD ENHANCEMENT TECHNIQUES;

ROUTING ALGORITHMS;

EID: 57649167189     PISSN: 0277786X     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1117/12.284707     Document Type: Conference Paper

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