The analysis of the stacked-surrounding gate transistor (s-sgt) dram for the high speed and low voltage operation

IEICE Transactions on Electronics

Volumn E81-C, Issue 9, 1998, Pages 1491-1498

  Endoh, Tetsuo ^a   Shinmei, Katsuhisa ^a   Sakuraba, Hiroshi ^a   Masuoka, Fujio ^a  

^a TOHOKU UNIVERSITY   (Japan)

Author keywords

Bit line capacitance; DRAM; SGT, S SGT

Indexed keywords

CAPACITANCE; ELECTRIC POTENTIAL; GATES (TRANSISTOR); NAND CIRCUITS;

STACKED-SURROUNDING GATE TRANSISTORS (S-SGT);

DYNAMIC RANDOM ACCESS STORAGE;

EID: 0032156558     PISSN: 09168524     EISSN: None     Source Type: Journal    
DOI: None     Document Type: Article

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