Impact of a Vertical Φ-Shape Transistor (V ΦT) Cell for 1 Gbit DRAM and Beyond

IEEE Transactions on Electron Devices

Volumn 42, Issue 12, 1995, Pages 2117-2124

  Maeda, Shigenobu ^b   Maegawa, Shigeto ^b   Ipposhi, Takashi ^b   Kuriyama, Hirotada ^b   Tanina, Osamu ^b   Inoue, Yasuo ^b   Nishimura, Tadashi ^b   Tsubouchi, Natsuro ^b   Nishimura, Hisayuki ^a  

^a Ryoden Semiconduct Syst Eng Corp   (Japan)

^b MITSUBISHI ELECTRIC CORPORATION   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

ELECTRODES; GATES (TRANSISTOR); RANDOM ACCESS STORAGE; SEMICONDUCTOR DEVICE STRUCTURES;

CHANNEL PLUG; DYNAMIC RANDOM ACCESS MEMORY (DRAM); VERTICAL SHAPE TRANSISTOR;

MOSFET DEVICES;

EID: 0029545790     PISSN: 00189383     EISSN: 15579646     Source Type: Journal    
DOI: 10.1109/16.477769     Document Type: Article

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