An Experimental DRAM with a NAND-Structured Cell

IEEE Journal of Solid-State Circuits

Volumn 28, Issue 11, 1993, Pages 1099-1104

  Hasegawa, Takehiro ^a   Takashima, Daisaburo ^a   Ogiwara, Ryu ^a   Ohta, Masako ^a   Shiratake, Shin ichiro ^a   Hamamoto, Takeshi ^a   Yamada, Takashi ^a   Aoki, Masami ^a   Ishibashi, Shigeru ^a   Oowaki, Yukihito ^a   Watanabe, Shigeyoshi ^a   Masuoka, Fujio ^a  

^a TOSHIBA CORPORATION   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

AMPLIFIERS (ELECTRONIC); CELLULAR ARRAYS; CMOS INTEGRATED CIRCUITS; INTEGRATED CIRCUIT LAYOUT; NAND CIRCUITS; SEMICONDUCTOR DEVICE STRUCTURES;

DYNAMIC RANDOM ACCESS MEMORY; STRUCTURED CELL; TIME DIVISION MULTIPLEX SENSE AMPLIFIER;

RANDOM ACCESS STORAGE;

EID: 0027694114     PISSN: 00189200     EISSN: 1558173X     Source Type: Journal    
DOI: 10.1109/4.245588     Document Type: Article

References (5)

1. H. Komiya, “Future technological and economic prospects for VLSI,” ISSCC Dig. Tech. Papers; pp. 16–19, Feb. 1993.
2. H. Kawagoe et al., “Minimum size ROM structure compatible with silicon-gate E/D MOS LSI,” IEEE J. Solid-State Circuits, vol. SC-11, pp. 360–364, June 1976.
3. F. Masuoka et al., “New ultra high density EPROM and flash EEPROM with NAND structure cell,” IEDM Tech. Dig., pp. 552–555, Dec. 1987.
4. K. Kimura et al., “A block-oriented RAM with half-sized DRAM cell and quasi-folded data-line architecture,” ISSCC Dig. Tech. Papers, pp. 106–107, Feb. 1991.
5. T. Hasegawa et al., “An experimental DRAM with a NAND-structured cell,” ISSCC Dig. Tech. Papers, pp. 46–47, Feb. 1993.