Dual layer bitline DRAM array with Vcc/Vss hybrid precharge for multi-gigabit DRAMs

IEEE Symposium on VLSI Circuits, Digest of Technical Papers

Volumn , Issue , 1996, Pages 190-191

  Nakano, H ^a   Takashima, D ^a   Tsuchida, K ^a   Shiratake, S ^a   Inaba, T ^a   Ohta, M ^a   Oowaki, Y ^a   Watanabe, S ^a   Ohuchi, K ^a   Matsunaga, J ^a  

^a TOSHIBA CORPORATION   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

AMPLIFIERS (ELECTRONIC); ELECTRIC CHARGE; ELECTRIC CURRENTS; FLIP FLOP CIRCUITS; GATES (TRANSISTOR); INTEGRATED CIRCUIT LAYOUT; INTEGRATED CIRCUIT TESTING; MOS DEVICES; SPURIOUS SIGNAL NOISE;

FLIP FLOP TRANSISTORS; GATE SOURCE VOLTAGE; SENSE AMPLIFIERS; SURROUNDING GATE TRANSISTOR; THRESHOLD VOLTAGE;

RANDOM ACCESS STORAGE;

EID: 0029725231     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (6)