Impact of Surrounding Gate Transistor (SGT) for Ultra-High-Density LSI's

IEEE Transactions on Electron Devices

Volumn 38, Issue 3, 1991, Pages 573-578

  Takato, Hiroshi ^a   Sunouchi, Kazumasa ^a   Okabe, Naoko ^a   Nitayama, Akihiro ^a   Hieda, Katsuhiko ^a   Masuoka, Fujio ^a  

^a TOSHIBA CORPORATION   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

ELECTRIC INVERTERS; INTEGRATED CIRCUITS, LSI; SEMICONDUCTOR DEVICES, MOS;

CMOS INVERTER; GATE-CONTROLLABILITY; STEEP CUTOFF CHARACTERISTICS; SURROUNDING GATE TRANSISTOR (SGT); ULTRA-HIGH-DENSITY LSI'S; VERY SMALL SUBSTRATE BIAS EFFECTS;

TRANSISTORS;

EID: 0026122410     PISSN: 00189383     EISSN: 15579646     Source Type: Journal    
DOI: 10.1109/16.75168     Document Type: Article

References (7)

1. S. Sawada, Y. Matsumoto, S. Shinozaki, and O. Ozawa, “Effects of field boron dose on substrate current in narrow channel LDD MOSFETs,” in IEDM Tech. Dig., pp. 778–781, 1984.
2. S. M. Sze, Physics of Semiconductor Devices, 2nd ed. New York, NY Wiley, 1981, p. 446.
3. J. P. Colinge, “Subthreshold slope of thin-film SOI MOSFET's,” IEEE Electron Device Lett., vol. EDL-7, pp. 244–246, 1986.
4. K. K. Young, “Analysis of conduction in fully depleted SOI MOSFET's,” IEEE Trans. Electron Devices, vol. 36, pp. 504–506, 1989.
5. K. Hieda, F. Horiguchi, H. Watanabe, K. Sunouchi, I. Inoue, and T. Hamaoto, “Effect of a new trench-isolated transistor using sidewall gates,” IEEE Trans. Electron Devices, vol. 36, pp. 1615–1619, 1989.
6. T. Mizuno, T. Higuchi, Y. Matsumoto, Y. Saitoh, S. Sawada, and S. Shinozaki, “High speed and highly reliable trench MOSFET with dual-gate,” in Proc. VLSI Symp., pp. 23–24, 1988.
7. K. Sunouchi, H. Takato, N. Okabe, T. Yamada, T. Ozaki, S. Inoue, K. Hashimoto, K. Hieda, A. Nitayama, F. Horiguchi, and F. Masuoka, “A surrounding gate transistor (SGT) cell for 64/ 256Mbit DRAMs,” in IEDM Tech. Dig., pp. 23–26, 1989.