3-Weight Pseudo Random Test Generation Based on a Deterministic Test Set for Combinational and Sequential Circuits

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Volumn 12, Issue 7, 1993, Pages 1050-1058

  Pomeranz, Irith ^a   Reddy, Sudhakar M ^a  

^a UNIVERSITY OF IOWA   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

COMBINATORIAL CIRCUITS; ELECTRIC FAULT LOCATION; RANDOM PROCESSES; SEQUENTIAL CIRCUITS; SHIFT REGISTERS; STATE ASSIGNMENT; STATISTICAL TESTS;

BUILT-IN-TEST; DETERMINISTIC TEST SET; LINEAR FEEDBACK SHIFT REGISTERS; WEIGHTED PSEUDO RANDOM TEST GENERATION;

LOGIC CIRCUITS;

EID: 0027629166     PISSN: 02780070     EISSN: 19374151     Source Type: Journal    
DOI: 10.1109/43.238041     Document Type: Article

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