Single-Transistor Latch in SOI MOSFET's

IEEE Electron Device Letters

Volumn 9, Issue 12, 1988, Pages 636-638

  Chen, C E Daniel ^a   Matloubian, Mishel ^a   Sundaresan, R ^a   Mao, B Y ^a   Wei, C C ^a   Pollack, Gordon P ^a  

^a TEXAS INSTRUMENTS   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

TRANSISTORS, FIELD EFFECT;

HIGH DRAIN BIASES; SILICON-ON-INSULATOR (SOI); SINGLE-TRANSISTOR LATCH; SOI MOSFET;

SEMICONDUCTOR DEVICES, MOSFET;

EID: 0024133319     PISSN: 07413106     EISSN: 15580563     Source Type: Journal    
DOI: 10.1109/55.20420     Document Type: Article

References (6)

1. S.M. Sze, Physics of Semiconductor Devices, 2nd ed. New York: Wiley, 1981, p. 493.
2. J.R. Davis, A.E. Glaccum, K. Reeson, and P.L.F. Hemment, “Improved subthreshold characteristics of n-channel SOI transistors,” IEEE Electron Device Lett., vol. EDL-7, no. 10, p. 570, 1987.
3. A. Boudou and B.S. Doyle, “Hysteresis I V effects in short-channel silicon MOSFET's,” IEEE Electron Device Lett., vol. EDL-8, no. 7, p. 300, 1987.
4. H.P. Zappe, R.K. Gupta, I. Sakai, and C. Hu, “Operation of CMOS devices with a floating well,” IEEE Trans. Electron Devices, vol. ED-34, no. 2, p. 335, 1987.
5. B.-Y. Mao, M. Matloubian, C.-E. Chen, R. Sundaresan, and C. Slawinski, “The effect of post-oxygen-implant annealing temperature on the channel mobilities of CMOS devices in oxygen-implanted silicon-on-insulator structures,” IEEE Electron Device Lett., vol. EDL-8, no. 7, p. 306, 1987.
6. M. Matloubian, C.-E. Chen, B.-Y. Mao, R. Sundaresan, and G. Pollack, “Analytical modeling of subthreshold region of SOI MOS-FETs with floating body,” presented at the IEEE SOS/SOI Workshop, Durango, CO, Oct. 1987 (to be published).