High-speed and low-power operation of a resonant tunneling logic gate MOBILE

IEEE Electron Device Letters

Volumn 19, Issue 3, 1998, Pages 80-82

  Maezawa, Koichi ^a,b   Matsuzaki, Hideaki ^a,c   Yamamoto, Masafumi ^a,c   Otsuji, Taiichi ^a,c  

^a IEEE   (Japan)

^b NAGOYA UNIVERSITY   (Japan)

^c NTT CORPORATION   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

CALCULATIONS; CURRENT VOLTAGE CHARACTERISTICS; ELECTRIC LOSSES; EQUIVALENT CIRCUITS; FABRICATION; HIGH ELECTRON MOBILITY TRANSISTORS; MATHEMATICAL MODELS; SEMICONDUCTING INDIUM PHOSPHIDE;

NEGATIVE DIFFERENTIAL RESISTANCE; RESONANT TUNNELING LOGIC GATE;

LOGIC GATES;

EID: 0032028977     PISSN: 07413106     EISSN: None     Source Type: Journal    
DOI: 10.1109/55.661171     Document Type: Article

References (14)

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