Depletion isolation effect of surrounding gate transistors

IEEE Transactions on Electron Devices

Volumn 44, Issue 12, 1997, Pages 2303-2305

  Terauchi, Mamoru ^a  

^a TOSHIBA CORPORATION   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

CURRENT VOLTAGE CHARACTERISTICS; DIFFUSION IN SOLIDS; SEMICONDUCTING SILICON; SEMICONDUCTOR DEVICE MANUFACTURE; SEMICONDUCTOR DEVICE STRUCTURES; SUBSTRATES;

SURROUNDING GATE TRANSISTORS (SGT);

GATES (TRANSISTOR);

EID: 0031365765     PISSN: 00189383     EISSN: None     Source Type: Journal    
DOI: 10.1109/16.644659     Document Type: Article

References (10)

1. H. Takato K. Sunouchi N. Okabe A. Nitayama K. Hieda F. Horiguchi and F. Masuoka High performance CMOS surrounding gate transistor (SGT) for ultra high density LSI's in IEDM Tech. Dig. 1988 p. 222.
2. K. Sunouchi H. Takato N. Okabe T. Yamada T. Ozaki S. Inoue K. Hashimoto K. Hieda A. Nitayama F. Horiguchi and F. Masuoka A surrounding gate transistor (SGT) cell for 64/256Mbit DRAM's in IEDM Tech. Dig. 1989 p. 23.
3. H. Takato K. Sunouchi N. Okabe A. Nitayama K. Hieda F. Horiguchi and F. Masuoka Impact of surrounding gate transistor (SGT) for ultra-high-density LSI's IEEE Trans. Electron Devices vol. 38 p. 573 1991.
4. A. Nitayama H. Takato N. Okabe K. Sunouchi K. Hieda F. Horiguchi and F. Masuoka Multi-pillar surrounding gate transistor (M-SGT) for compact and high-speed circuits IEEE Trans. Electron Devices vol. 38 p. 579 1991.
5. S. Miyano M. Hirose and F. Masuoka Numerical analysis of a cylindrical thin-pillar transistor (CYNTHIA) IEEE Trans. Electron Devices vol. 39 p. 1876 1992.
6. M. Terauchi A. Nitayama F. Horiguchi and F. Masuoka A surrounding gate transistor (SGT) gain cell for ultra high density DRAM's in Dig. Tech. Papers 1993 Symp. VLSI Technol. p. 21.
7. H. Pein and J. D. Plummer Performance of the 3-D PENCIL flash EPROM cell and memory array IEEE Trans. Electron Devices vol. 42 p. 1982 1995.
8. H. I. Hanafi S. Tiwari S. Burns W. Kocon A. Thomas N. Garg and K. Matsushita A scalable low power vertical memory in IEDM Tech. Dig. 1995 p. 657.
9. J. P. Colinge Subthreshold slope of thin-film SOI MOSFET's IEEE Electron Device Lett. vol. EDL-7 p. 244 1986.
10. M. Yoshimi H. Hazama M. Takahashi S. Kambayashi T. Wada K. Kato and H. Tango Two-dimensional simulation and measurement of high-performance MOSFET's made on a very thin SOI film IEEE Trans. Electron Devices vol. 36 p. 493 1989.