Multi-Pillar Surrounding Gate Transistor (M-SGT) for Compact and High-Speed Circuits

IEEE Transactions on Electron Devices

Volumn 38, Issue 3, 1991, Pages 579-583

  Nitayama, Akihiro ^a   Takato, Hiroshi ^a   Okabe, Naoko ^a   Sunouchi, Kazumasa ^a   Hieda, Katsuhiko ^a   Horiguchi, Fumio ^a   Masuoka, Fujio ^a  

^a TOSHIBA CORPORATION   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

ELECTRIC INVERTERS; ELECTRODES; SEMICONDUCTOR DEVICES, MOS;

COMPACT/HIGH-SPEED CIRCUITS; HIGH SHRINKAGE FEATURE; M-SGT CMOS INVERTER CHAIN; MESH-STRUCTURED GATE ELECTRODE; MULTI-PILLAR SURROUNDING GATE TRANSISTOR (M-SGT);

TRANSISTORS;

EID: 0026117513     PISSN: 00189383     EISSN: 15579646     Source Type: Journal    
DOI: 10.1109/16.75169     Document Type: Article

References (5)

1. S. Sawada, Y. Matsumoto, S. Shinozaki, and O. Ozawa, “Effects of field boron dose on substrate current in narrow channel LDD MOSFETs,” in IEDM Tech. Dig, 778, 1984.
2. H. Takato, K. Sunouchi, N. Okabe, A. Nitayama, K. Hieda, F. Horiguchi, and F. Masuoka, “High performance CMOS surrounding gate transistor (SGT) for ultra high density LSIs,” in IEDM Tech. Dig., p. 222, 1988.
3. K. Hieda, F. Horiguchi, H. Watanabe, K. Sunouchi, I. Inoue, and Hamamoto, “New effects of trench isolated transistor using side-wall gates,” in IEDM Tech. Dig., p. 736, 1987.
4. T. Mizuno, T. Higuchi, Y. Matsumoto, Y. Saitoh, S. Sawada, and S. Shinozaki,“High speed and highly reliable trench MOSFET with dual-gate,” in VLSI Symp. Dig., p. 23, 1988.
5. T. Sakurai and T. Iizuka, “Gate electrode RC delay effects in VLSI's,” IEEE Trans. Electron Devices, vol. ED-32, no. 2, p. 370, 1985.